neese@adaptex.UUCP (10/31/89)
>How does the AT Bus (8/16-bit memory and I/O expansion slots) work >with respect to multiple bus masters? In particular, please describe >the bus signal protocol in detail. > ><STUFF DELETED> The bus master stuff isn't well documented at all in any At tech ref manual I have found, but here is a quickie on how it works. The requestor drives the BR (Bus request) signal on the bus and waits for BG (Bus grant) to go true. Once this has occurred, the Master signal must be driven before BG goes false, or the requstor must assert BR again. The Master signal is held by the requestor until it releases the bus to the CPU, or IOCHRDY goes false. If IOCHRDY goes false then the master should release the bus. IOCHRDY can be ignored, but it is not wise to do so. Once the requestor has the bus it can hold it forever. There is no premptive state that can occur to stop it on the AT bus, so a bus master must be well behaved in this regard. The bus master does drive all memory RW and IO RW signals, just as the CPU would, as it has full control of the machine during master time. Some software also has to do some work. Before the master DMA can be turned on, the on board DMA must be mask off and put into cascade mode or the transfers will fail. This is a very brief description of bus master, if you would like more details then drop me a line. 'adaptex' will be arond for another week. Roy Neese Adaptec Central Field Applications Engineer UUCP @ {texbell,attctc}!cpe!adaptex!neese merch!adaptex!neese