werner@aecom.yu.edu (Craig Werner) (02/07/90)
In article <959@watserv1.waterloo.edu>, ssingh@watserv1.waterloo.edu ($anjay "lock-on" $ingh - Indy Studies) writes: > Along the same note, I am hoping someone can help me with several questions > relating to 386sx vs. 386dx architectures. > > 1. I have a DTK 386sx (ppm-1630 is the technical name) with 2 megs of 100 > ns drams. ?) Are these memory chips the same as that used in 386dx chips? > > > 3. Does anyone know of any 486 boards with 100 nsec DRAMS? > If it is done right, then 32-bit memory is usually arranged in multiples of 36 (counting parity) chips. So if the 2M is 8 sets of 256K, it is is a 386DX configuration. If it is 2 sets of 1M, then probably not, although, not all architectures are optimal. Similarly, 486 boards with 100ns DRAMs are probably a bad design. Since the slowest 486 is 25MHz, this leaves only 40ns for memory access without a wait state. A cache can only do so much. A common solution is to interleave the memory and alternate the refresh of the even/odd bits. This allows 80ns RAM to be used with essentially no wait state. Of course, this requires 8 banks of chips (or multiple thereof) for optimal performance, twice as much as above. Of course, multiples of 4 will work (multiples of 36 chips as above) but they force a wait state. -- Craig Werner (future MD/PhD, 4.5 years down, 2.5 to go) werner@aecom.YU.EDU -- Albert Einstein College of Medicine (1935-14E Eastchester Rd., Bronx NY 10461, 212-931-2517) "If I don't see you soon, I'll see you later."