nicholls@bcsaic.UUCP (Bill Nicholls) (02/10/90)
This is a second post to a larger distribution. (does anybody read this group in "pnw" ?) A local vendor is selling a 25MHz '386 system with 1 Mb ram '0' wait state 32Kb cache memory What's the point of having both? Either I'm missing something, or the presence of the cache should slow the system down. Perhaps the cache returns data in one clock cycle instead of two? Doesn't seem likely. Perhaps the memory is only eight bits wide, that would be a waste. William H. Nicholls - nicholls@atc.boeing.com Boeing Defense & Space Group - nicholls@ee.washington.edu (let ((*standard-disclaimers* t)) ... )
Ralf.Brown@B.GP.CS.CMU.EDU (02/16/90)
In article <20154@bcsaic.UUCP>, nicholls@bcsaic.UUCP (Bill Nicholls) wrote: }A local vendor is selling a 25MHz '386 system with } } 1 Mb ram '0' wait state } 32Kb cache memory } }What's the point of having both? }Either I'm missing something, or the presence }of the cache should slow the system down. It's the cache that is making the RAM '0' wait state, unless the vendor is using 1M of 40ns chips, which means static RAMs, which means $$$$$$$ (I would not at all be surprised to hear that 40ns SRAMs are over a thousand bucks a meg, particularly since there are no 1mbit SRAMs yet). -- UUCP: {ucbvax,harvard}!cs.cmu.edu!ralf -=- 412-268-3053 (school) -=- FAX: ask ARPA: ralf@cs.cmu.edu BIT: ralf%cs.cmu.edu@CMUCCVMA FIDO: Ralf Brown 1:129/46 "How to Prove It" by Dana Angluin Disclaimer? I claimed something? 14. proof by importance: A large body of useful consequences all follow from the proposition in question.
victor@hercule.cs.concordia.ca (KRAWCZUK victor) (02/17/90)
In article <25dc04c8@ralf> Ralf.Brown@B.GP.CS.CMU.EDU writes: > >It's the cache that is making the RAM '0' wait state, unless the vendor is >using 1M of 40ns chips, which means static RAMs, which means $$$$$$$ (I >would not at all be surprised to hear that 40ns SRAMs are over a thousand >bucks a meg, particularly since there are no 1mbit SRAMs yet). > -- Does anyone out there think this type of chip (40 ns SRAM) will eventually replace the ubiquitous DRAM chips in PC's? If yes, any guesstimates?? Will mass produced DRAMS go below 70 ns??? What is the physical limit???? Just wondering, -Victor.
dhinds@portia.Stanford.EDU (David Hinds) (02/18/90)
In article <1860@clyde.concordia.ca>, victor@hercule.cs.concordia.ca (KRAWCZUK victor) writes: > Does anyone out there think this type of chip (40 ns SRAM) will eventually > replace the ubiquitous DRAM chips in PC's? If yes, any guesstimates?? > Will mass produced DRAMS go below 70 ns??? What is the physical > limit???? > SRAM will never replace DRAM for normal bulk main memory. SRAM requires either twice or four times as many transistors as the same amount of DRAM - I don't quite remember which. The extra circuit complexity is also a problem, I think. In any case, in terms of how difficult a chip is to make (= price, sort of), an SRAM of a given size will equal about 2 to 4 DRAMs of the same size. This seems to be confirmed by the progress and prices of SRAM chips vs. DRAMs recently. The speed improvements of DRAM's haven't fallen that far behind increases in CPU demands on memory. They are starting to now - which is why an increasingly large fraction of PC's will have static RAM caches. The speed of a chip is due to a combination of switching times and signal propagation delays. So, if you just make a chip smaller, it should get faster. I'm not sure what the physical limit is for silicon-based IC's, but it must be within an order of magnitude of present speeds (which means we are close, judging from the rate of improvement of technology). - David Hinds dhinds@popserver.stanford.edu
david@metapyr.UUCP (David Relson) (02/20/90)
DRAM's will always be cheaper than SRAM's for a given amount of storage. DRAMs store a value as a minute charge (a tiny capacitor). Since capacitors lose their charge over time, DRAMs need to be refreshed periodically. SRAMs use four capacitors to form a flip-flop which will remember "forever" (or until power is turned off). This means that when the state of the art is a 4Mb DRAM, the biggest available SRAM is 1Mb (both have 4 million capacitors). Concerning speed, SRAMs tend to be quicker. Part of the reason is that to minimize physical size, DRAMs make double use of address pins, i.e. half the address is fed to the DRAM, then the other half, i.e. the row and column addresses. This keeps things slower. SRAMS tend to have sufficient pins so that this is not necessary.
bbesler@vela.acs.oakland.edu (Brent Besler) (02/20/90)
I have seen 60 ns 1 Mbit DRAM chips and SIMM/SIPP's made from them at a few mail order placesd in the last month. The fastest SRAM chips I have seen are 25 ns, but read in Byte that Toshiba is developing 15 ns ones. I doubt SRAM will ever replace DRAM in micros. It is too expensive. In the fastest mainframes, the memory is all SRAM. On the Cray-XMP, they have to use special interleaving procedures to get the ram to keep up with the CPU even with its very fast memory. The Cray uses ECL(emmiter coupled logic) RAM, I believe, which is probably close to 10 ns.
keithe@tekgvs.LABS.TEK.COM (Keith Ericson) (02/21/90)
In article <20154@bcsaic.UUCP> nicholls@bcsaic.UUCP (Bill Nicholls) writes: >This is a second post to a larger distribution. >(does anybody read this group in "pnw" ?) Both the pnw and na postings made it to tektronix. But I don't know the answer to your questions... kEITHe
rob@prism.TMC.COM (02/22/90)
nicholls@bcsaic.UUCP writes: >A local vendor is selling a 25MHz '386 system with > 1 Mb ram '0' wait state > 32Kb cache memory >What's the point of having both? >Either I'm missing something, or the presence >of the cache should slow the system down. This is a little late, but there's a simple answer to this. Namely, the main memory doesn't have 0 wait states. It's pretty common practice these days to advertise systems as having 0 wait state memory when they really don't. What they usually mean is that the main memory operates with 0 wait states some of the time (as with paged or interleaved memory), or that the memory performance is equivalent to that of a slower machine running at 0 wait states. Either way, it's misleading. Building a 386 machine that truly runs without wait states would require using static RAM (or very fast dynamic RAM) for main memory, and would be difficult to do at reasonable cost. Dell put out such a machine a few years ago that used static RAM throughout. It was fast, but a good caching system can offer nearly the same performance at far lower cost, and that's the route most vendors take now.
cs4g6ag@maccs.dcss.mcmaster.ca (Stephen M. Dunn) (02/27/90)
In article <9275@portia.Stanford.EDU> dhinds@portia.Stanford.EDU (David Hinds) writes:
$ SRAM will never replace DRAM for normal bulk main memory. SRAM requires
$either twice or four times as many transistors as the same amount of DRAM -
$I don't quite remember which. The extra circuit complexity is also a problem,
$I think. In any case, in terms of how difficult a chip is to make (= price,
$sort of), an SRAM of a given size will equal about 2 to 4 DRAMs of the same
$size. This seems to be confirmed by the progress and prices of SRAM chips
$vs. DRAMs recently. The speed improvements of DRAM's haven't fallen that far
$behind increases in CPU demands on memory. They are starting to now - which
$is why an increasingly large fraction of PC's will have static RAM caches.
DRAM requires one transistor per bit; I'm not sure how many SRAM requires,
although I do recall that in at least some SRAMs of the early 80s they used
six transistors per bit. This alone means that DRAMs will always, given the
same technology, have much higher densities than SRAMs. And don't be fooled
too much by the price argument ... sure, the more complex the chip, the lower
the yield on a wafer is, and so the higher the price must be, but supply and
demand also plays a very important role. Look at the prices for, say, a
25 MHz 80387 and tell me how much of that is really manufacturing cost.
There was a PC back about a year or two after the AT was introduced that
had a 1M SRAM memory for no-wait-state performance, but I don't think anyone
is doing that any longer (especially since ATs no longer need SRAM for 0-WS).
$ The speed of a chip is due to a combination of switching times and signal
$propagation delays. So, if you just make a chip smaller, it should get faster.
$I'm not sure what the physical limit is for silicon-based IC's, but it must be
$within an order of magnitude of present speeds (which means we are close,
$judging from the rate of improvement of technology).
Yes, the limit for silicon is about 0.1 micron ... currently, most chips
are fabbed (as far as I know ... which isn't that far) at between 0.5 and 2
microns. GaAs can go quite a bit smaller than that, but of course they
won't be reaching the limits of GaAs for a long, long time since they're
still struggling with getting good yields out of it for not-too-complex
chips.
--
Stephen M. Dunn cs4g6ag@maccs.dcss.mcmaster.ca
<std_disclaimer.h> = "\nI'm only an undergraduate!!!\n";
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