jim@cdp.UUCP (03/01/90)
Does anyone have any information on exactly (in excruciating detail) what happens after the CPU receives a hardware interrupt and before the time the interrupt handler is entered. In what order do context saves, etc. happen? In what order to registers get put on the stack? What else goes on the stack and in what order? Any information or a pointer to a detailed discussion of this subject would be greatly appreciated. The environment is PC-DOS v3.3. Thanks, Jim Wampler ..!uunet!pyramid!cdp!jim ..!hplabs!cdp!jim jim@cdp.UUCP
johnl@esegue.segue.boston.ma.us (John R. Levine) (03/02/90)
In article <140700021@cdp> jim@cdp.UUCP writes: >Does anyone have any information on exactly (in excruciating detail) >what happens after the CPU receives a hardware interrupt and before the time >the interrupt handler is entered. If it's an external interrupt, the device yanks its interrupt line which is typically connected to an 8259A interrupt controller. That controller in turn signals the CPU via its INTR input. If the CPU has interrupts enabled, it then issues a special bus cycle to acknowledge the interrupt and read an 8-bit interrupt type from the 8259A. On a PC this number will generally be between 10 and 17, corresponding to IRQ lines 0 to 7. It then multiplies the interrupt type by 4 to get the address from which it will load the interrupt routine, e.g. IRQ 2 is interrupt 12 whose interrupt routine address is at location 48. A request on the NMI line is always type 2 but is otherwise similar. An internally generated interrupt gets its type number from the INT instruction or, if it's a divide error, INTO, or other internal trap, a fixed number depending on the type of the interrupt. Then the processor pushes the flags register, the IP (instruction pointer), and the CS (code segment) on the current stack. It turns off the interrupt flag. It loads the IP and CS from the two words at the address computed above. The rest is up to you. Your routine has to save any registers that it uses, probably switch to another stack since you can't count on the existing stack having much room, do whatever it does, restore the registers, and do an IRET. If your interrupt handler is written in C, you will need to set up the segment registers to match what the C compiler expected. Some compilers, notably Turbo C have an "interrupt" keyword on a routine that tells it to save all of the registers. Unfortunately, since it doesn't switch stacks this is of limited use and you usually still need some assembler glue. If the interrupt was due to INTR, you need to execute an OUT instruction to the 8259A to tell it to dismiss the interrupt just before the IRET. When you tell DOS to install an interrupt routine, all it does is to stuff the address of your interrupt routine into the hardware table of interrupt addresses. DOS 3.3 has some sort of stack switching code for its own use but it's not clear if one can take advantage of it. If you are in protected mode on a 286, 386, or 486, the response to an interrupt is considerably more complicated, involving segment and task switching. For details on that, see Intel's programmer's reference manuals. -- John R. Levine, Segue Software, POB 349, Cambridge MA 02238, +1 617 864 9650 johnl@esegue.segue.boston.ma.us, {ima|lotus|spdcc}!esegue!johnl "Now, we are all jelly doughnuts."
risto@tuura.UUCP (Risto Lankinen) (03/02/90)
jim@cdp.UUCP writes: >Does anyone have any information on exactly (in excruciating detail) >what happens after the CPU receives a hardware interrupt and before the time >the interrupt handler is entered. In what order do context saves, >etc. happen? In what order to registers get put on the stack? What ... >Jim Wampler There was a very good article, called "How the 8259A PIC Manages External I/O Devices" in the Microsoft Systems Journal, May'89 (Vol 4 #3) on this subject. terveisin: Risto Lankinen -- Risto Lankinen / product specialist *************************************** Nokia Data Systems, Technology Dept * 2 2 * THIS SPACE INTENTIONALLY LEFT BLANK * 2 -1 is PRIME! Now working on 2 +1 * replies: risto@yj.data.nokia.fi ***************************************
rob@prism.TMC.COM (03/03/90)
jim@cdp.UUCP asks: >Does anyone have any information on exactly (in excruciating detail) >what happens after the CPU receives a hardware interrupt and before the time >the interrupt handler is entered. In what order do context saves, >etc. happen? In what order to registers get put on the stack? What >else goes on the stack and in what order? Any information or a >pointer to a detailed discussion of this subject would be greatly >appreciated. The environment is PC-DOS v3.3. Any of the Intel reference manuals for the 8086 line would have detailed information on this subject. In brief (assuming the interrupt enable flag is set) the CPU 1) waits for the current instruction to complete. 2) issues two interrupt acknowledge cycles 3) reads a byte from the bus indicating which interrupt is being requested (this byte should be placed on the bus by the requesting device, usually an interrupt controller, during the second INTA cycle) 4) Looks up the handler address in the interrupt table (the above byte, multiplied by 4, provides the offset into the table) 5) Pushes the flags onto the stack 6) Clears the interrupt enable and trap flags 7) Pushes CS onto the stack 8) Loads CS with the segment address of the interrupt handler 9) Pushes IP onto the stack 10) Loads IP with the offset address of the interrupt handler At this point, the transfer to the handler is complete. Non-maskable interrupts are a bit different; the state if the interrupt flag is ignored, and the handler is always vector 2.