levine@ics.uci.edu (David Levine) (05/28/90)
I heard that it is not a good idea to use DRAM that is rated much faster than required, e.g., 70 ns in place of 120 ns. Ignoring the price difference, is this true? If so, why? -- David L. Levine, Dept. of ICS Internet: levine@ics.uci.edu University of California, Irvine BITNET: levine@ucivmsa Irvine, CA 92717 UUCP: ucbvax!ucivax!levine
dhinds@portia.Stanford.EDU (David Hinds) (05/29/90)
In article <7613@canterbury.ac.nz> PHYS169@canterbury.ac.nz (Mark Aitchison, U of Canty; Physics) writes: >In article <2660AECB.29143@paris.ics.uci.edu>, levine@ics.uci.edu (David Levine) writes: >> I heard that it is not a good idea to use DRAM that is rated much faster >> than required, e.g., 70 ns in place of 120 ns. Ignoring the price >> difference, is this true? If so, why? >> >As I understand it, there are two reasons: >(a) there might be "junk" on the bus for a short time that is not a problem to > the slow memory chips, but could be to fast chips >(b) faster chips usually consume more power, introduce current pulses on the > power supply lines that are more synchronised, etc. These things should only apply if the two different speeds of DRAM's have been made from different masks. I think I read on the net that all the normal varieties are made from the same mask regardless of speed, and are sorted by speed after testing. So there would be no difference between a 70ns chip driven at 120ns, and a "native" 120ns chip running at that speed. When a chip needs to be redesigned to reach its rated speed, then these compatibility issues would become important. I think that even 60ns chips are still made on the same lines as the slower versions. -David Hinds dhinds@popserver.stanford.edu
janh@hplsla.HP.COM (Jan Hofland) (05/29/90)
There is NO reason not to use DRAMs rated faster than the required application. The power consumed is primarily a function of the operating frequency and has nothing to do with how fast the device will actually go. A 70ns device and a 120 ns device from the same vendor (assuming the same process) will consume virtually the same power in a particular application. With regard to timing, when reading, there is a design minimum access time. Any device faster than this minimum will still meet spec and, in fact, give more margin. When writing, the data must be available when the system generates column address strobe and any device which meets the design minimums will work. Regards, Jan Hofland
PHYS169@canterbury.ac.nz (Mark Aitchison, U of Canty; Physics) (05/29/90)
In article <2660AECB.29143@paris.ics.uci.edu>, levine@ics.uci.edu (David Levine) writes: > I heard that it is not a good idea to use DRAM that is rated much faster > than required, e.g., 70 ns in place of 120 ns. Ignoring the price > difference, is this true? If so, why? > As I understand it, there are two reasons: (a) there might be "junk" on the bus for a short time that is not a problem to the slow memory chips, but could be to fast chips (Chip specs often quote times when input address & data lines must be stable by, as well as times when output lines will have stabilised to their correct values). If the board was designed for slow chips, it *might not* work with significantly faster chips. (b) faster chips usually consume more power, introduce current pulses on the power supply lines that are more synchronised (sharper and more severe) - so the bypass capacitors on the board might not be adequate, and can have different loading (capacitance and resistance) on the bus which was probably designed to compensate for standing waves only when certain chips were in place. Mark Aitchison.
dlow@hpspcoi.HP.COM (Danny Low) (05/30/90)
>I heard that it is not a good idea to use DRAM that is rated much faster >than required, e.g., 70 ns in place of 120 ns. Ignoring the price >difference, is this true? If so, why? I use faster DRAMs all the time and have had no problems. If there is any problems, the speed difference must be rather larger than the 20-50 ns difference in the DRAMs I use. Danny Low "Question Authority and the Authorities will question You" Valley of Hearts Delight, Silicon Valley HP SPCD dlow%hpspcoi@hplabs.hp.com ...!hplabs!hpspcoi!dlow