mmm@cup.portal.com (Mark Robert Thorson) (06/05/90)
In studying the tech ref to the PC/XT, I notice that one of the slots has restricted timing. This is because it's got an extra layer of buffers between itself and the local bus of the CPU, so the address arrives later and any data has to be returned earlier. Are incompatibilities with the timing for slot J8 a common problem? Do most people just leave J8 alone, or what?