crash@pro-colony.UUCP (John Stephen III) (02/16/88)
On Feb 1 Scott Kempf asked what the linearization in the IIGS's SHR
display mode was. From what I've observed (doing memory fills, changing the
linearization state, and studying the differences) the linearization works as
follows:
In the linear-ized mode (C029:41 or C029:C1) the buffer is ordered from
E1/2000 to E1/9FFF with the first byte of the SHR display at E1/2000, the
second byte at E1/2001, etc... In this mode the scan-line bytes run from
E1/9D00 to E1/9DFF and the palette information runs from E1/9E00 to E1/9FFF.
In the non-linear mode (C029:01 or C029:81) the buffer is ordered in a way
that is similar to the 80 column text screen. It works something like this:
The EVEN bytes of the display buffer (linear-mode even addresses E1/2000 to
E1/9FFE) are stored from E1/2000 to E1/5FFF. The ODD bytes of the buffer
(linear-mode odd addresses E1/2001 to E1/9FFF) are stored from E1/6000 to
E1/9FFF. This means the display bit-map is stored from E1/2000 to E1/5E7F and
from E1/6000 to E1/9E7F, the scan-line bytes are stored from E1/5E80 to
E1/5EFF and from E1/9E80 to E1/9EFF, and the palette data is from E1/5F00 to
E1/5FFF (all of the blue/green bytes) and from E1/9F00 to E1/9FFF (all of the
red bytes).
Since all of the bytes are uniquely accounted for (no byte is at two
different addresses and no byte is missing from an address) it doesn't matter
which mode is active while an application is running (as long as the mode
doesn't change, a value written to any of the buffer addresses will be the
same value that gets returned when reading the same address).