AWCTTYPA@UIAMVS.BITNET ("David A. Lyons") (08/03/88)
>Date: Sun, 31 Jul 88 23:10:24 GMT >From: David Whitney <whitney@THINK.COM> >Subject: Re: Fast/Slow screen RAM >Note also that the processor slows when the 5.25" disk is on. Try >this: call-151, C0E9<ret> (drive turns on - make sure it doesn't have >disk inside!), 300L - note the printout speed - C0E8<ret> (drive >turns off), 300L - zing! much faster. It may also slow down for the >3.5" but I don't think so (have absolutely no idea, really). Very true, but *only* if bit 2 of $C036 is turned on! Otherwise the system continues to run at full speed! (I knew this before but re-learned it the hard way when I helped a friend write a patch to "trick" his system into using his port-6 5.25 drive as if it were in slot 7, since his hard-drive interface was hard-coded to run from slot 6 only.) There are similar bits for slots 4, 5, and 7. I haven't looked at the slot 5 firmware lately...but it can do what it wants; if it wants to run full-speed, all it needs to do is clear the right bit in $C036 if it isn't already! ----- Re: clock speeds possible with NNN-ns RAM chips. Things are trickier than they seem! I have no idea whether a technique like the following will be used in the IIgs+, if there is one, but it's something than *can* be done to get speeds higher than you would otherwise be able to. For the sake of argument, let's say I want to run my machine about 4 times faster than people think I ought to be able to given the speed of my RAM chips. Fine: I divide my RAM chips into 4 (or a multiple of 4) groups. Then I wire them up so that addresses that are multiples of 4 are in the first group; addresses 1 higher than those are in the second group, etc. [In other words, for any Group Theory people out there, we partition the memory locations using the equivalence relation xRy <==> x=y(mod 4). x and y are in the same partition if and only if x and y both have the same remainder when divided by 4.] Since during any given memory access only ONE of the 4 groups of chips is being read from, we can take the opportunity to pre-fetch, or at least START to pre-fetch, the next 3 bytes from the other 3 groups of chips. Of course, there are gobs of details I left out [some because I don't want to write a whole book on this topic & most because I don't even realize they are problems], but you get the idea. I believe the "slow RAM" for super-hires *does* use a technique like this, but with only 2 groups of chips. Odd addresses in one, even addresses in another. The video circuitry has a major advantage over the processor: it always knows which locations it's going to want next. It always scans memory in the same sequence [within a particular display mode, of course] to display on the screen. >David Whitney, MIT '90 DISCLAIMER: Nobody knows what I'm up >{out there}!harvard!think!whitney to. Don't blame them for my actions >whitney@think.com nor me for theirs. >^^^^^ will be changing before 1989 is here. Don't depend on it after 1/1/89. --David A. Lyons a.k.a. DAL Systems PO Box 287 | North Liberty, IA 52317 BITNET: AWCTTYPA@UIAMVS CompuServe: 72177,3233 GEnie mail: D.LYONS2
gwyn@smoke.ARPA (Doug Gwyn ) (08/03/88)
In article <8808012324.aa05390@SMOKE.BRL.MIL> AWCTTYPA@UIAMVS.BITNET ("David A. Lyons") writes: >Since during any given memory access only ONE of the 4 groups of >chips is being read from, we can take the opportunity to pre-fetch, >or at least START to pre-fetch, the next 3 bytes from the other 3 >groups of chips. Interleaving memory is of course one of the standard ways to increase its effective transfer rate. You do need to worry about synchronization issues, since much memory access is not sequential. A generally more effective approach is to has a modest high-speed cache. On the IIGS the graphics page might be treated as special "write-through" addresses.