Bruce_Kahn@maytag.ceo.dg.COM (11/06/87)
It appears to me that the Zip chip will be great if you do lots of
processor intensive work (ie graphics) but not that great if you do
I/O intensive (ie a BBS). The 4MHz clock is strictly internal to the
chip so that all other mother board and cards are not affected, or so
it sounds. Am I correct in my assumptions?
Bruce Kahnkamath@reed.UUCP (Sean Kamath) (11/09/87)
In article <47.002420@adam.DG.COM> Bruce_Kahn%MAYTAG.CEO.DG.COM@adam.dg.COM writes: > > It appears to me that the Zip chip will be great if you do lots of >processor intensive work (ie graphics) but not that great if you do >I/O intensive (ie a BBS). The 4MHz clock is strictly internal to the >chip so that all other mother board and cards are not affected, or so >it sounds. Am I correct in my assumptions? > > Bruce Kahn According to the tech conference that was held on the Zip CHip in San Francisco, the chip will now let you read from a Sider at the Sider's speed. Apperently the Sider has to wait for the // to fetch the data. I do know that the Sider (10 & 20 meg) use a pre SCSI called SASI (for Shugart Associates Serial Interface...SCSI was developed by Shugart) and is one of the reason's why Siders are fast. In anycase, I asuume (probably incorrectly) that this also applies to SCSI drives. . . (if they aren't DMA) Which means a BBS should speed up. (You are running a hard drive, *aren't* you?) Sean Kamath -- UUCP: {decvax allegra ucbcad ucbvax hplabs ihnp4}!tektronix!reed!kamath CSNET: reed!kamath@Tektronix.CSNET || BITNET: reed!kamath@Berkeley.BITNET ARPA: tektronix!reed!kamath@Berkeley <or> reed!kamath@hplabs US Snail: 3934 SE Boise, Portland, OR 97202 (I hate 4 line .siut-sB
jla@hogbbs.Fidonet.Org (Slartibartfast) (09/01/88)
To: ALL
I was wondering.....I am in the process of buying a NO-SLOT clock for my
//e and was considering in the near future buying a Zip Chip. Will the
added speed of the Zip Chip also speed up the SMT Clock? I really don't
want to buy one of those bulky clocks that takes up a whole slot. Right
now I own a dinosaur Mountain Computers Clock and the thing doesn't store
the Year. I am running a BBS and that tends to mess up some of my files.
Could somebosy help me here.
Thanks,
Jim Anderson
--
Slartibartfast via The Heart of Gold UUCP<>Fidonet Gateway, 1:263/42
UUCP: ...!psuvax1!psuhcx!hogbbs!jla
Internet: jla@hogbbs.Fidonet.Orgtmetro@lynx.northeastern.EDU (09/02/88)
> I am in the process of buying a NO-SLOT clock for my //e and was > considering in the near future buying a Zip Chip. > Will the added speed of the Zip Chip also speed up the SMT Clock? No. The No-Slot-Clock (manufactured by Dallas Semiconductor - dst. by SMT) has its own internal frequency reference. Besides the Zip Chip's method of acceleration does not affect the system clock or speed external to the CPU. Be warned that the No-Slot-Clock may not work with the Zip Chip for other (yet unknown) reasons. I have a No-Slot-Clock installed in my //c which does not opperate when I have a W65C802 CPU installed in place of the 65C02. Western design Center (creator of the 65C802/816) is looking into the problem. ___________ ./ Tom Metro \_____________________________________________________________. | _ _ | | INET: tmetro@pro-angmar.uucp --/\/\_| |_| '- DigiTell, Inc. | | ARPA: crash!pnet01!pro-angmar!tmetro@nosc.mil Newton, MA | | UUCP: [ihnp4 sdcsvax nosc]!crash!pnet01!pro%angmar!tmetro | |_Alternate: tmetro@lynx.northeastern.edu__________________________________| "I think I was kidding" - Reagan
david@jc3b21.UUCP (David Quarles) (09/05/88)
> Be warned that the No-Slot-Clock may not work with the Zip Chip for other > (yet unknown) reasons. I have a No-Slot-Clock installed in my //c which > does not opperate when I have a W65C802 CPU installed in place of the 65C02. > Western design Center (creator of the 65C802/816) is looking into the > problem. WILL THE ZIP CHIP work with an enhanced ][e that has the SMT clock ?
matthew@sunpix.UUCP ( Sun NCAA) (09/06/88)
In article <457@jc3b21.UUCP>, david@jc3b21.UUCP (David Quarles) writes: > > WILL THE ZIP CHIP work with an enhanced ][e that has the SMT clock ? I think the correct question is "Will the SMT Clock work in an enhanced //e with ZIP CHIP". The only limitation I can think of is that ZIP CHIP cashe-ing must be disabled for the memory locations used by the Zip Chip. I've got a DS1216E in my //c and use my own "custom" software. I got the DS1216E locally for $16 and have had zero trouble with it. Bar-ring cashe-ing, I can't think of any problems with a No-Slot-Clock / Zip Chip combo. -- Matthew Lee Stier (919) 469-8300| Sun Microsystems --- RTP, NC 27560| "Wisconsin Escapee" uucp: {sun, rti}!sunpix!matthew |
kamath@reed.UUCP (Sean Kamath) (09/21/88)
In article <memo.44082@lynx.northeastern.edu> tmetro@lynx.northeastern.EDU writes: >No. The No-Slot-Clock (manufactured by Dallas Semiconductor - dst. by >SMT) has its own internal frequency reference. Besides the Zip Chip's >method of acceleration does not affect the system clock or speed external >to the CPU. True enough, but, as stated previously, if it happens to cache in the wrong place, it will destroy the "wakeup" sequnce on the a0 line. (or is it the a4 line?) >Be warned that the No-Slot-Clock may not work with the Zip Chip for other >(yet unknown) reasons. I have a No-Slot-Clock installed in my //c which >does not opperate when I have a W65C802 CPU installed in place of the 65C02. >Western design Center (creator of the 65C802/816) is looking into the >problem. Yes, I had the same problem. I don't think it is "anyone's" fault. By that I mean I talked to SMT (Who at the time had just hired a mr. Sanders of "Understanding the Apple . . ." fame.) and they had not a clue as to what was wrong. Timing chart *are* just a bit off, but: It works just fine in micro #2 with a 65802 in it. Soooooo... I think it's your MMU. "Huh?" he grunts. I have looked and looked, but nowhere have I found documentation on it: Appearantly (Dennis Domms told me this at the last applefest), a few of the MMU's in the //e's were a little screwy. They could cause timing errors. Since the MMU is directly responsible for handling the R\W line, this *might* be the problem. Since I can't get any docs on this "bug", all I can say is: Try another MMU. Maybe it'll work. If it *does*, then PLEASE send me the stuff (i.e. part number and all that) for the chip, we can compare it to mine, and issue a "warning" about this. > Tom Metro Sean Kamath PS I'm Back! PPS And I'm on BITNET! Weeeeee -- UUCP: {decvax allegra ucbcad ucbvax hplabs ihnp4}!tektronix!reed!kamath CSNET: reed!kamath@Tektronix.CSNET || BITNET: kamath@reed.BITNET ARPA: reed!kamath@PSUVAX1.CS.PSU.EDU US Snail: 3934 SE Boise, Portland, OR 97202-3126 (I hate 4 line .sigs!)