V112PDL5@ubvmsc.cc.buffalo.edu (12/07/88)
Alain Raynaud <ULMO031@FRORS12. BITNET> writes
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And once again, it is very well designed : a
coprocessor just adds new instructions, and it is EXACTLY as if they were
instructions of the main processor. So, with the 68881, you add FSIN,
FCOS, FSQRT, etc... and it is transparent to the programmer, and fast.
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Actually, according to the statements from the 65816's designer, there
is an similar function on the '816:
cop #
If memory serves, it will be a pre-byte for instructions to an on chip
FPU in the '832. So, for instance, cop $30, might be FSIN, FCOS, FSQRT....
Granted, it requires 16 bits but transparency is retained. Furthermore,
machines with meager '816s can be retroffited with a software version.
This is made possible because the instruction on the '816 now performs
a software interrupt. A program would determine the presence of a '816
and install the proper vectroughthe GS' built in COP Manager.
No unnecessary branching to provide full compatability!
The only down note about this is that the '832 won't be ready until
1992! Of course, I haven't heard anything about this since it came out.
Are there any Western Design Center employies out there?
I recall that someone, somewhere, once wrote a critique of the 65816.
If it's available, I would certainly like to see it.
BTW, we shall soon see if a '816 at the save Mhz as a 68000 will have
better performance. The Transwarp GS, supposedly, will offer 7 Mhz initially
but eventually 10 Mhz will be available. It won't be a true test until
an '816 is run without the need of caching, of course.
BTW, the 68000 was outperformed by a microprocessor built by a college
professor and his graduate students. They used RISC technology as I
recall.
- Mark Cromwell
v112pdl5@ubvmsd
markc@pro-starbase
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