AWCTTYPA@UIAMVS.BITNET ("David A. Lyons") (12/15/88)
>Date: Fri, 9 Dec 88 10:53:28 est >From: DSEAH%WPI.BITNET@MITVMA.MIT.EDU >Subject: MEGA II >[...] I don't have the Hardware Ref with me right now, but let me >postulate this: The Mega II controls, among other things, video >updates. The Mega II, as a II-in-a-box, is so complicated that it >just barely creeps along at 1MHz. The slow side of the GS runs at 1MHz, and exists in the first place, for a very good reason (and complexity is not it!). The old Apple II video modes (text, lores graphics, 80-col text, double-lores graphics, hires graphics, and double-hires graphics) are designed so that the display hardware needs to read from the display memory (which is in Slow RAM on the GS) once each microsecond to get data to feed to the screen. When the CPU was running at 1MHz, this worked out perfectly, since the 6502 only needs access to its RAM during half of the clock cycle (which is 1 microsecond with a clock speed of 1MHz). No cycle stealing of any kind was needed with a 1MHz CPU. As I understand the GS, the FPI (Fast Processor Interface) synchronizes the fast and slow sides of the system by making the 65816 wait, during access to slow RAM, for the appropriate part of the slow side's clock cycle. By "access to slow RAM" I mean a read or write of a location from $E00000 to $E1FFFF, or a Write (not a read) to an area of fast RAM that happens to be shadowed into slow RAM; shadowed RAM normally includes the text screen and $Cxxx I/O locations, and also the hires/double-hires areas except when ProDOS 16 or GS/OS is active. --David A. Lyons bitnet: awcttypa@uiamvs DAL Systems CompuServe: 72177,3233 P.O. Box 287 GEnie mail: D.LYONS2 North Liberty, IA 52317 AppleLinkPE: Dave Lyons