hentosh@amethyst.bucknell.EDU (03/21/89)
I have a question concerning the clock on the IIgs during a read/write to
shadowed RAM. When the CPU does a write to the shadowed RAM is it at 1MHz
during the whole instruction or only part of the instruction? And if it is
only part of the instruction, is there a table anywhere that shows how many
cycles it is slow for? (If you have one in a file could you post it on
Apple2-L?) I also understand that when the processor is running fast it
has to wait (at the most) one slow clock cycle for it to get into sync with
the MegaII (approx 1 microsec. (on the average 0.5 microsec?)). If you
have several instructions that write to shadowed RAM consecutively, does
this synchronization have to take place for each instruction? How long does
the processor stay at 1MHz after accessing slow RAM?
Any information to the above questions would be most appreciated.
Thanks,
Bob.
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