toddpw@tybalt.caltech.edu (Todd P. Whitesel) (04/18/89)
i am trying to figure out how the vgc in the //gs operates (partly out of
curiosity, but mostly because i'm investigating ideas for CS projects)
and have turned up some really strange anomalies (read: i don't get it yet)
1. how does the vgc read in the control and palette information?
2. how does the slow RAM skewering work?
3. how does the vgc get 32 bits every 1MHZ and display them with a 16MHZ dot
clock?
i can guess how number 1 works but that's all it is, just a guess. (control
byte then 32 palette bytes)
the slow RAM would have to be skewed somehow but why are main/aux swapped
from $6000-$9FFF ? how does that let the vgc read in linearly mapped displays
any faster (or is that not the idea)?
lastly, how does the vgc read the pixel data if it has a 16 bit hardware bus
but needs 32 bits every 1MHZ cycle? does it steal cpu accesses (clock 0 high)
or does it page mode the DRAMs but how can it do that if the mega II controls
RAS and CAS ?
any gs gurus out there? explanations would be appreciated.
toddpw @ romeo.caltech.edu
toddpw @ caltech.bitnet