SEWALL@UCONNVM.BITNET (Murph Sewall) (08/24/89)
>I deeply suspect that there is another GS waiting in the wings... > >Now would be a good time for Apple to pre-announce the existence of a >Souped-Up GS... I've been at this "rumor" stuff long enough to have a "confidential source" or two. One recently told me that a "souped up" IIgs is NOT in the offing for this year. The reason is cost. At the moment there simply is NO SOURCE of faster 65816's in *sufficient volume* to meet the demand (or viewed another way, for Apple to be able to produce a IIgs in large enough production quantities to make a competitive system price possible). A IIgs that would cost more than a Mac IIci (about $6,000) is not what we have in mind is it? Note how much difficulty Appied Engineering is having meeting orders for TWGS's (and how many are delivered with a promise of a faster CPU "later") along with the difficulty Zip is having simply getting their accelerator on the market. AE and Zip are dealing with order quantites which are a fraction of the volume Apple would require to make a IIgs+ viable. I suppose Apple *could* pull an IBM move and announce a machine that would be almost impossible to actually obtain. That would simply *thrill* the customers wouldn't it (and Apple wouldn't make any profit on it either)? My source DID indicate that Apple was able to announce the ROM 3 IIgs now instead of waiting for AppleFest is that they DO have some more interesting (if not completely astonishing ;-) software AND hardware to unveil next month (and not just the Mac IIci and LapMac either). Western Design is promising production quantities of the 65832 next year. Maybe we'd all be better of if Apple invested their energy on developing a 32 bit Apple II (?) Murph Sewall Vaporware? ---> [Gary Larson returns 1/1/90] Prof. of Marketing Sewall@UConnVM.BITNET Business School sewall%uconnvm.bitnet@cunyvm.cuny.edu [INTERNET] U of Connecticut {psuvax1 or mcvax }!UCONNVM.BITNET!SEWALL [UUCP] (203) 486-5246 [FAX] (203) 486-2489 [PHONE] 41 49N 72 15W [ICBM] The opposite of artificial intelligence is genuine stupidity! -+- I don't speak for my employer, though I frequently wish that I could (subject to change without notice; void where prohibited)
shankar@bedrock.SRC.Honeywell.COM (Subash Shankar) (08/26/89)
In article <8908240922.aa13041@SMOKE.BRL.MIL> SEWALL@UCONNVM.BITNET (Murph Sewall) writes: >Western Design is promising production quantities of the 65832 next year. >Maybe we'd all be better of if Apple invested their energy on developing >a 32 bit Apple II (?) Would we? I suppose this would result in improvements in handling 24-bit addresses, but since the 65832 still has only a 8-bit databus, I wouldn't expect much improvements for most code. And I'm not holding my breath waiting for an on-time announcement of production quantities of the 65832. --- Subash Shankar Honeywell Systems & Research Center voice: (612) 782 7558 US Snail: 3660 Technology Dr., Minneapolis, MN 55418 shankar@src.honeywell.com srcsip!shankar
SEWALL@UCONNVM.BITNET (Murph Sewall) (08/28/89)
>As a person with some good sources myself, and a rumor collector like >you, may I suggest that you do a little double checking about the >status of the Mac IIci....... Yes, it was to be announced at the 9/20 >thing at Universal theater, but from what I am getting, it has now been >placed on a back burner, Apple possibly yeilding to the Wall Street >pressure NOT to do it this year, where the experts fear it will KILL the >market for the IIcx before Apple gets back it's R&D money etc.. Anything's possible, I suppose. After all, IBM delayed announcing the portable Model 70 for a few weeks after pictures and reviews of it had appeared in the trade press. However, I don't think delaying the IIci for financial or market reasons at this juncture would make much sense. First, the machine (including its performance characteristics and price) is no secret. Those who are going to wait for the IIci in preference to the IIcx will wait anyway. The IIci has some features besides greater speed that the IIcx doesn't, but the machines are similar enough that I doubt it's really possible to divide R&D investments among the two, besides Wall Streeters generally are more sophisticated about 'sunk costs.' Holding up the IIci will simply delay realizing a return on the investment developing the 25 MHz Mac. Another reason I expect to see the IIci this Fall is Apple plans to introduce a whole new line of Mac II's after January First (the principal difference will be a 20 MHz NuBus). Delaying the IIci will simply push back the whole schedule. From here, that doesn't appear condusive to maximizing the cash flow (which is what recovering R&D is all about). There may be technical reasons for delaying the IIci (FCC certification, production line glitches, etc.) but if Wall Street is given as an excuse, I'll suspect a "smoke screen." >Will you be at the user group breakfeast at Applefest??? No, but you may see our Club's giant economy size cherub (and Apple Ambassador -- or whatever title they've given him) George Carbonell there. Murph Sewall Vaporware? ---> [Gary Larson returns 1/1/90] Prof. of Marketing Sewall@UConnVM.BITNET Business School sewall%uconnvm.bitnet@cunyvm.cuny.edu [INTERNET] U of Connecticut {psuvax1 or mcvax }!UCONNVM.BITNET!SEWALL [UUCP] (203) 486-5246 [FAX] (203) 486-2489 [PHONE] 41 49N 72 15W [ICBM] The opposite of artificial intelligence is genuine stupidity! -+- I don't speak for my employer, though I frequently wish that I could (subject to change without notice; void where prohibited)
brianw@microsoft.UUCP (Brian Willoughby) (08/28/89)
In article <29229@srcsip.UUCP> shankar@bedrock.UUCP (Subash Shankar) writes: >In article <8908240922.aa13041@SMOKE.BRL.MIL> SEWALL@UCONNVM.BITNET (Murph Sewall) writes: > >>Western Design is promising production quantities of the 65832 next year. >>Maybe we'd all be better of if Apple invested their energy on developing >>a 32 bit Apple II (?) > >Would we? >I suppose this would result in improvements in handling 24-bit addresses, >but since the 65832 still has only a 8-bit databus, I wouldn't expect >much improvements for most code. And I'm not holding my breath >waiting for an on-time announcement of production quantities of the >65832. >--- Don't get me wrong, I'm a 16 bit 6502 fan, but I've been wondering just how much trouble is takes to use the different data sizes on the 65C8xx. Every time you switch sizes, you have to flip the M or X bits using a 2 byte, 3 cycle instruction. Also, I would assume that you have to use a consistent method of calling subroutines (i.e. always having M and X set to 16 bit on subroutine entry). But what if you are in the middle of some 8 bit string manipulation code, and want to make a call to 'printf' for output? If you've chosen a 16 bit default between subroutine calls, then you have to switch out of 8 bit mode, only to reselect it when you print out the 8 bit characters. The way the instruction set has ended up, I hate to see what the 65832 does to utilize 32 bit data. Anyone have any benchmarks for the 65C816 which can be compared to the other processors out there? The 80386 has the same trouble when selecting register data sizes. The old 8086 had 8 and 16 bit opcodes, which pretty much filled up the available opcode patterns. Now that 32 bit registers are available (but not always used) Intel had to add an opcode size override, which makes only the immediately following instruction use a different size (i.e. mov ax,memory becomes 32 bit when it used to be a 16 bit instruction). As you can probably guess, code that is largely 32 bit would suffer a great deal if a byte prefix were added to every 32 bit opcode, so to complicate matters even further, Intel has a bit in the segment descriptor which selects the default size for that segment of code. Now, in a 32 bit default segment, the opcode size override prefix selects 16 bit data. Arrrgghhhhh! At least the 65816 stays in 16 bit mode once you select it, instead of only affecting one instruction at a time. But which method works out better? I don't know... Brian Willoughby UUCP: ...!{tikal, sun, uunet, elwood}!microsoft!brianw InterNet: microsoft!brianw@uunet.UU.NET or: microsoft!brianw@Sun.COM Bitnet brianw@microsoft.UUCP
joseph@elbereth.rutgers.edu (Seymour Joseph) (08/29/89)
I would like to see some better hardware math in a 6502 family chip. Yep the 8086 may not be as efficient with cycles but it doesn't have to do integer multiplication through repetetive addition like the the 65xxx family. Seymour
dlyons@Apple.COM (David Lyons) (08/29/89)
In article <Aug.28.19.03.36.1989.10846@elbereth.rutgers.edu> joseph@elbereth.rutgers.edu (Seymour Joseph) writes: >I would like to see some better hardware math in a 6502 family chip. >Yep the 8086 may not be as efficient with cycles but it doesn't have >to do integer multiplication through repetetive addition like the the >65xxx family. > >Seymour You have a valid point. Note that "repeated addition" may be a misleading way to describe how to do multiplication on a 6502/etc: it would be silly to to M or N additions to multiply MxN. Instead, the number of additions would typically be the number of *bits* turned on in either M or N, and there would be some bit shifting. --Dave Lyons, Apple Computer, Inc. | DAL Systems AppleLink--Apple Edition: DAVE.LYONS | P.O. Box 875 AppleLink--Personal Edition: Dave Lyons | Cupertino, CA 95015-0875 GEnie: D.LYONS2 or DAVE.LYONS CompuServe: 72177,3233 Internet/BITNET: dlyons@apple.com UUCP: ...!ames!apple!dlyons My opinions are my own, not Apple's.