ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET (09/06/89)
Hi,
I'm having this trouble with a parallel interface I'm building for my //e. I
have some experience building things (MIDI-interface, RS-232, sound, you know)
and have never had any trouble. Now I'm working on a card consisting of 2 VIA's
(6522) and I just can't get it to work !!
The design is pretty straightforward:
2 VIA's and one 74LS138 3-to-8-decoder for address-decoding:
A4 - A5 - A6 connected to input lines,
A7 to first enable (active low),
_________
IO-SELECT to second enable (active low),
third enable to +5V (active high).
Output 1 of the LS138 is connected to VIA-1, output 2 to VIA-2.
A0 to A3 are connected to R(-egister)S(-elect)0 to RS3 of both VIA's.
As a clock I'm just using Phi-0 (I also tried inverted Phi-1 but that
didn't work either). No patching done to the clock.
The interface should be in the address range $C700 to $C7FF (if I put it in
slot 7; VIA 1 : $C700-$C70F, VIA 2: $C710-$C71F) but there's nothing there !!
Is there something I don't know about and is causing me this trouble ? Have I
overlooked something?? Could someone shed some light onto this subject ???
Any help is _very_ appreciated ... thanks in advance.
Robert Belleman, ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET
ROBBEL%NKIVXH.SURFNET@SARA.NL
PSI%02041291011::ROBBELpaul@athertn.Atherton.COM (Paul Sander) (09/07/89)
In article <8909060935.aa25446@SMOKE.BRL.MIL>, ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET writes: > Hi, > > I'm having this trouble with a parallel interface I'm building for my //e. > > [Stuff omitted] > > The design is pretty straightforward: > > 2 VIA's and one 74LS138 3-to-8-decoder for address-decoding: > > A4 - A5 - A6 connected to input lines, > A7 to first enable (active low), > _________ > IO-SELECT to second enable (active low), > third enable to +5V (active high). > Output 1 of the LS138 is connected to VIA-1, output 2 to VIA-2. > > A0 to A3 are connected to R(-egister)S(-elect)0 to RS3 of both VIA's. So far so good. > As a clock I'm just using Phi-0 (I also tried inverted Phi-1 but that > didn't work either). No patching done to the clock. When I built my 6522 peripheral card, this is where I had problems. In my Apple ][ Plus (and I assume also its successors) the -IOSEL line is low only during the second half of the clock cycle. Because of this, the VIA's setup times are not met. > The interface should be in the address range $C700 to $C7FF (if I put it in > slot 7; VIA 1 : $C700-$C70F, VIA 2: $C710-$C71F) but there's nothing there !! Yep, this is what'll happen. I never was able to repair the problem with 1 MHz VIAs without adding a jumper to my motherboard which forced -IOSEL to widen to the entire clock cycle. This patch is not recommended because it probably will cause glitches elsewhere, such as causing two card to compete for the $C800 ROM space because a glitch enabled something accidently. The way I solved the problem was to buy a 2 MHz VIA, wire it as you did, but clock it off the 2 MHz asymmetric clock (I forget its name here). This card has worked flawlessly for me for years. > [stuff omitted] > > Robert Belleman, ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET > ROBBEL%NKIVXH.SURFNET@SARA.NL > PSI%02041291011::ROBBEL -- Paul Sander (408) 734-9822 | If a machine is powerful enough paul@Atherton.COM | to have a DWIM button, why bother {decwrl,sun,pyramid}!athertn!paul | with the button? -- Eric Black
dlyons@Apple.COM (David Lyons) (09/08/89)
In article <8909060935.aa25446@SMOKE.BRL.MIL> ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET writes: > 2 VIA's and one 74LS138 3-to-8-decoder for address-decoding: > A4 - A5 - A6 connected to input lines, > A7 to first enable (active low), > _________ > IO-SELECT to second enable (active low), > third enable to +5V (active high). > Output 1 of the LS138 is connected to VIA-1, output 2 to VIA-2. > A0 to A3 are connected to R(-egister)S(-elect)0 to RS3 of both VIA's. > As a clock I'm just using Phi-0 (I also tried inverted Phi-1 but that > didn't work either). No patching done to the clock. >The interface should be in the address range $C700 to $C7FF (if I put it in >slot 7; VIA 1 : $C700-$C70F, VIA 2: $C710-$C71F) but there's nothing there !! Sounds pretty reasonable to me. When you say "nothing is there" for $C700-1F, are you getting the same random-ish stuff you get when the card isn't plugged in at all, or something else? You didn't mention the D0-D7 signals, but I assume you've just connected them straight to the VIAs. (I don't have the 6522 specs right in front of me...what are you doing with the clock? Just running it to "clock" inputs on the 6522s?) --Dave Lyons, Apple Computer, Inc. | DAL Systems AppleLink--Apple Edition: DAVE.LYONS | P.O. Box 875 AppleLink--Personal Edition: Dave Lyons | Cupertino, CA 95015-0875 GEnie: D.LYONS2 or DAVE.LYONS CompuServe: 72177,3233 Internet/BITNET: dlyons@apple.com UUCP: ...!ames!apple!dlyons My opinions are my own, not Apple's.
Dick@cup.portal.com (dick a wotiz) (09/08/89)
> I'm having this trouble with a parallel interface I'm building for my //e. I > have some experience building things (MIDI-interface, RS-232, sound, you know) > and have never had any trouble. Now I'm working on a card consisting of 2 VIAs > (6522) and I just can't get it to work !! I remember running into this a while back... I seem to recall that the 6502 applies the address and R/W signals at the start of phi0, but the 6522 latches these lines on the same rising edge. What I did was delay phi0 by a small amount, by running it through four sections of a 74LS04 inverter before running it to the 6522. That way, the 6522 had enough set-up time on the address lines before latching them in. You could probably get away with a RC delay also, if you don't have enough spare gates to use. Dick Wotiz dick@portal.com
ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET (09/08/89)
(I have posted this before but didn't suscribe to the list ... smart eh ? ...
so I'm trying again ... sorry about this)
Hi,
I'm having this trouble with a parallel interface I'm building for my //e. I
have some experience building things (MIDI-interface, RS-232, sound, you know)
and have never had any trouble. Now I'm working on a card consisting of 2 VIA's
(6522) and I just can't get it to work !!
The design is pretty straightforward:
2 VIA's and one 74LS138 3-to-8-decoder for address-decoding:
A4 - A5 - A6 connected to input lines,
A7 to first enable (active low),
_________
IO-SELECT to second enable (active low),
third enable to +5V (active high).
Output 1 of the LS138 is connected to VIA-1, output 2 to VIA-2.
A0 to A3 are connected to R(-egister)S(-elect)0 to RS3 of both VIA's.
As a clock I'm just using Phi-0 (I also tried inverted Phi-1 but that
didn't work either). No patching done to the clock.
The interface should be in the address range $C700 to $C7FF (if I put it in
slot 7; VIA 1 : $C700-$C70F, VIA 2: $C710-$C71F) but there's nothing there !!
Is there something I don't know about and is causing me this trouble ? Have I
overlooked something?? Could someone shed some light onto this subject ???
Any help is _very_ appreciated ... thanks in advance.
Please respond by email. I will post any responses to the list if anyone's
interested.
Robert Belleman, ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET
ROBBEL%NKIVXH.SURFNET@SARA.NL
(PSI%02041291011::ROBBEL)tbopp@uhccux.uhcc.hawaii.edu (Tom Bopp) (09/09/89)
In article <21981@cup.portal.com> Dick@cup.portal.com (dick a wotiz) writes: >> I'm having this trouble with a parallel interface I'm building for my //e. I >> have some experience building things (MIDI-interface, RS-232, sound, you know) >> and have never had any trouble. Now I'm working on a card consisting of 2 VIAs >> (6522) and I just can't get it to work !! > >I remember running into this a while back... I seem to recall that >the 6502 applies the address and R/W signals at the start of phi0, >but the 6522 latches these lines on the same rising edge. >What I did was delay phi0 by a small amount, by running it through >four sections of a 74LS04 inverter before running it to the 6522. >That way, the 6522 had enough set-up time on the address lines >before latching them in. You could probably get away with a >RC delay also, if you don't have enough spare gates to use. > >Dick Wotiz dick@portal.com I saw your note re/ problems with a 6522 interface, and I saw Paul Sander's response about the clock. If you can find it, get a copy of "Apple II Assembly Language" by Marvin L. De Jong. It was published by Sams in 1982 and may be in a library near you. ISBN 0-672-21894-1, and in our university library call no. QA 76.8.S63 D44. Chapter 9 is called "Programming with the 6522". The following circuit is shown (but not explained) as part of a wire-wrap project for the reader on page 221: CHIP IS 74LS05 or equiv. +5 V (Apple 25) ------------------------------------------ | | | | | | 4.7K 4.7K 1K | | | | | | 13 12 | 5 6 | 11 10 | ------|>-----------|>-----------|>----------------- Phi 1 in | | Clock out to (Apple 38) | | 6522 pin 25 -----||------- 10 pF If Paul Sanders is right, this is a circuit that may fix you up. good luck. tom
martyp@pnet02.gryphon.com (Martin Peckham) (09/09/89)
The common solution the the 6522 VIA is to delay one of the 'phases'. It's
been a long time and my memory doesn't recall whether it's phase 1 or phase 2
clock signal. Usinge a D-type flip-flop clocked with the 7meg clock will delay
this signal by about 140 nanoseconds, which is about right.
Marty
UUCP: {ames!elroy, <routing site>}!gryphon!pnet02!martyp
INET: martyp@pnet02.gryphon.comsedwards@tybalt.caltech.edu (Stephen A. Edwards) (09/10/89)
I have built three cards now which connect 6522s to the Apple II bus. A trick
is required to actually get the two buggers to talk. The problem is as follows:
The IOSEL' line (decoding the Cn00 space) becomes valid on the rising edge of
the phase 0 clock. However, the 6522 needs its chip select lines valid shortly
/before/ the rising edge of the clock. (I don't have a data sheet handy with
the exact time. Suffice it to say it is in excess of three gate delays.)
There are about three solutions to this problem:
1) Do the address decoding on-board. The address lines become valid much, much
earlier than the IOSEL' line. This is a bad idea, however, because it makes
the card slot dependent, or relies on dipswitches to select it. Ugh. This is
precisely the sort of thing which will make the hardware incompatible with
future Apple IIs, as well.
2) Delay the rising edge of the phase 0 clock. This would solve the problem,
but most garden variety 6522s require a symmetric 1 MHz maximum clock.
3) Delay both edges of the clock. This is the solution that I have seen two
commercial cards ( the Mockingboard, and a generic 6522 card ) use. A
circuit conditions the phase 0 clock in the following manner:
+5 +5 +5
| | |
> +--|(----+ > >
< | | < <
|\ > | |\ | > |\ >
| \ | | | \ | | | \ |
phase 1 ---| >O---+-+--| >O-+-+----| >O-+-- phase 0 to 6522
| / | / | /
|/ |/ |/
1/6 74LS05 1/6 74LS05 1/6 74LS05
This is an /ugly/ trick, but when the capacitor and resistor values are chosen
correctly, it works very well. Note that these are open-collector inverters,
which makes the circuit a little more predictable.
The 6522 card I have now exhibits a strange symptom: (I don't have the
capacitor right yet) When I put it in my IIgs, it works perfectly, AS LONG AS
THE MEMORY EXPANSION CARD IS NOT INSTALLED.
Ah, the joys of digital logic...
-Stephen A. Edwards
sedwards@tybalt.caltech.eduROBBEL%NKIVXH.SURFNET@HASARA5.BITNET ("Robert Belleman, Amsterdam") (09/11/89)
>In article <8909060935.aa25446@SMOKE.BRL.MIL> > ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET writes: >> 2 VIA's and one 74LS138 3-to-8-decoder for address-decoding: >> A4 - A5 - A6 connected to input lines, >> A7 to first enable (active low), >> _________ >> IO-SELECT to second enable (active low), >> third enable to +5V (active high). >> Output 1 of the LS138 is connected to VIA-1, output 2 to VIA-2. >> A0 to A3 are connected to R(-egister)S(-elect)0 to RS3 of both VIA's. >> As a clock I'm just using Phi-0 (I also tried inverted Phi-1 but that >> didn't work either). No patching done to the clock. >>The interface should be in the address range $C700 to $C7FF (if I put it in >>slot 7; VIA 1 : $C700-$C70F, VIA 2: $C710-$C71F) but there's nothing there !! > >Sounds pretty reasonable to me. When you say "nothing is there" for $C700-1F, >are you getting the same random-ish stuff you get when the card isn't plugged >in at all, or something else? I get the same random stuff if the card is un-plugged. >You didn't mention the D0-D7 signals, but I assume you've just connected them >straight to the VIAs. What!? You mean I have to connect D0-D7 ??? Sorry. Just kidding; I have: straight to the VIA's, no buffers. >(I don't have the 6522 specs right in front of me...what >are you doing with the clock? Just running it to "clock" inputs on the 6522s?) _ Yep, I just connected it to the 'E' input of the 6522. I think I'll have a go at that little circuit-hack Stephen, Dick and Tom were talking about. I'm pretty sure now it's a clock problem. I'll let you guys know if it turned out. Thank you all very much for your help, Dick, Tom, Dave, Stephen and all others who have replied but I haven't received yet ... Robert Belleman, the Netherlands Cancer Institute Amsterdam. ------------------------------------------------------------------------------- 'He whom whispers their | ROBBEL%NKIVXH.SURFNET@HASARA5.BITNET fate into the ears of | ROBBEL%NKIVXH.SURFNET@SARA.NL lobsters is bound to | ROBBEL@VAXH.NKI.NL get nipped.' | PSI%02041291011::ROBBEL -------------------------------------------------------------------------------