dseah@wpi.wpi.edu (David I Seah) (12/06/89)
I have been thinking of trying to do a graphics hardware project on my
IIGS based on some stuff I've been doing in school. There is a chip
called the TMS34070 Color Palette chip (from TI) that looks like it
could emulate all IIGS superhires modes and beyond, including fill and
scanline palettes. It also uses video RAM, so the graphics could even
be fast!
But where to put the frame buffer? I'd like to put it in its own 64K
bank of memory. Is all the reserved space from bank $80 up sacred?
I'm not interested in marketing the board, just grabbing some space to
play with. I figured I could choose a bank somewhere in the reserved
address space and decode for it off the address bus. Is there any
inherent danger in attempting this? (other than ignoring the meaning
of "Reserved", that is :)
Or perhaps I could shadow writes to the existing SHR buffer@012000.
As long as I have SHR shadowing turned off, all writes would be at
full speed. This scheme would seem to be simpler than the previous one.
(BTW, ignore that previous post in which I asked about gsRAM alleged
ability to use 1 chip at a time. I imagine it could be done, with
some kind of serial->parallel latch and a LOT of waiting around. But
that would be silly, as someone pointed out)
--
Dave Seah | O M N I D Y N E S Y S T E M S - M | Internet: dseah@wpi.wpi.edu
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