[comp.sys.apple] Speedy WDC Chips

brianw@microsoft.UUCP (Brian Willoughby) (11/15/89)

In article <8911100901.aa28335@SMOKE.BRL.MIL> UD041948@VM1.NODAK.EDU (Joe Carlin) writes:
>Are they just really stupid in the head to work together enough on it or
>what?  I can't believe that.  People say that a 7 Mhz TransWarp GS is the
>best investment they ever made, can you imagine what 10 Mhz will do?  I
>mean, the only, and I mean the_very one and only reason_ I'm holding out
>of buying a TransWarp is because they don't have the 10 Mhz version.
>
>Joe

Concerning the three companies working together, I don't know what their
problem is.  If Apple Co., AE and WDC would all sit down and plan the
development of the 65C8xx, then I'm sure the performance would be more
advanced than it is now.  WDC just isn't large enough to gamble money by
overproducing 65C816 chips, hoping that someone will pay for them.  AE
seems like a sturdy company, but they are still very small: they can't
foot the entire bill, either.  Apple has the bucks, but I think that they
are scared to death by the way they handled the recent RAM shortage and
wildly fluctuating RAM prices.  If Apple would only consider that there
is no single best way to handle all IC sources, and stop treating 65xxx
processors as if they were RAM chips (i.e. potential liabilities if
prices drop), then they could invest in WDC and get what their user base
wants (needs).

I'm not claiming to know about markets, but I don't see how investing in
WDC could be anything but a good idea for Apple.  RAM chips have MANY
suppliers in several countries, and any one can undercut the other or
dump old stock.  WDC is currently the ONLY maker of the 65C8xx line, so
there is no danger of the wildly fluctuating prices which might ruin a
good investment.  Even if another company were to start up in the 65C8xx
line, they still couldn't threaten to damage any investment that Apple
might make in WDC.  Basically, while investing in a particular RAM
manufacturer opens a company up to the possibility of becoming unable to
compete with other computer manufacturers (i.e. when the prices drop and
they are stuck with relatively expensive materials), investing in the
only source of a component is actually insurance for the future as well
as a good way to advance the performance of a product.

Well, I'm off the soapbox on that subject.

I don't see any reason not to buy the TransWarp GS.  If you have a GS,
then you can't lose anything by purchasing one now.  The replacement
processor is less than $20, and the crystal is the only other hardware
that determines the speed.  Why don't you thank AE for designing for the
future and buy one now?  Your purchase can only help AE and the Western
Design Center keep up their enhancements.  Compared to the current $280
price tag, $20 (or less) is a small price to pay for the higher speed.
Besides, you get to enjoy the TransWarp until then!

At least you aren't in my boat.  Because of the design of the original
TransWarp, I will never be able to speed up beyond 3.58 MHz - not without
buying an entirely new card.  I have a 10 MHz 65C802, but nowhere to use
it.  If I ever get a GS, I'll be happy that AE learned how to allow user
upgrades to the TransWarp GS as processors get faster.  So I would buy a
TransWarp GS, and upgrade as higher speeds become available.  If everyone
refused to buy a product because something better was on the way, then no
technical product line would ever make any money for a company and they
would have to shut down.  The TransWarp GS is NOT the ONLY AE product
that has been improved, just think about what might have happened if
nobody bought AE's early products!

Brian Willoughby
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krb20699@uxa.cso.uiuc.edu (11/16/89)

     I think AE is doing a good job of letting it's customers change the
card's speed with new chips and crystals.  AE is one of the better Apple II
supporting companies.
     The only limit to what AE can do is the IIgs's architecture, or so I 
hear.  If there is some way Apple could make the IIgs run with a higher
clock rate (i.e. >10Mhz) including the ROM, RAM, and possibly releasing
the 1 Mhz timing restriction on "pre-gs" I/O.  I am against Apple supplying
the IIgs with a standard clock rate greater than 6Mhz: the machine would be
too expensive, IMHO, and could cut into sales to people who don't need the
enhanced clock rate.
     I think AE and WDC could do their jobs a lot better if Apple were to
plan ahead and make the GS capable of speeding up without the current limit-
ations.  I think that putting enhancements of this kind in the hands of third-
party developers would be a better choice than to give Apple the "respons-
ibility."  I plan on getting a TWGS @7Mhz when I have some money, but I still
keep seeing the 12Mhz machines floating around.  :-)~  If that's as fast
as the gs will go (not that it's slow, mind you) I can't help but see some
problems with upgrading the gs any further.
     I'm a humble CS major, so I'm not sure what the above hardware mods would
entail, but I've seen many suggestions that could answer the problems (e.g.
seperate 1Mhz timer for the cards, combo 8-16 bit cards as in IBM/clones,
etc.)  And I'm not criticizing anyone: I think everything being done so far 
with clock speed, chips, and all the input in this file is great.

InterNet.......krb20699@uxa.cso.uiuc.edu      |     Ken Brownfield............
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lunatic@ucscb.UCSC.EDU (Lunatic) (11/16/89)

In article <9032@microsoft.UUCP> brianw@microsoft.UUCP (Brian Willoughby) writes:
>I'm not claiming to know about markets, but I don't see how investing in
>WDC could be anything but a good idea for Apple.  RAM chips have MANY
>suppliers in several countries, and any one can undercut the other or
>dump old stock.  WDC is currently the ONLY maker of the 65C8xx line, so
>there is no danger of the wildly fluctuating prices which might ruin a
>good investment.  Even if another company were to start up in the 65C8xx
>line, they still couldn't threaten to damage any investment that Apple
>might make in WDC.  Basically, while investing in a particular RAM
>manufacturer opens a company up to the possibility of becoming unable to
>compete with other computer manufacturers (i.e. when the prices drop and
>they are stuck with relatively expensive materials), investing in the
>only source of a component is actually insurance for the future as well
>as a good way to advance the performance of a product.
>
   \_/
    |ou've made a few mistakes, here.  WDC is NOT the only maker of
65816s.  Where do you think Apple gets the 65c816s it uses in the IIGS?
Certainly not WDC.  If Apple got their 65c816s from WDC, do you think
that shouting match between Jean Louis Gasse' and Bill Mensch at
AppleFest San Francisco would have happened?  (I was there, and it was
the BEST part of the entire keynote. :)  No, Apple gets their parts
from some other company that licenses the technology from WDC and
manufactures the parts for a much lower price.  Whatever company that is
(probably some south Asian entity) does not have the technology to
manufacture 65c816s at speeds much higher than 3 Mhz.  If Apple were to
invest in WDC, it would take a BIG risk that none of the other companies
that manufacture 65c816s (there are quite a few) could manufacture
higher speed processors at any time in the near future for prices lower
than WDC's.  This chance is slim to none.  I personally doubt that
Apple will EVER purchase any large quantities of chips from WDC.
Pricewise, WDC just can't compete with the cheap labour and materials
that south Asian companies build their products with.  Apple is a
business, and whether we like it or not, the driving force behind any
business is the bottom line.

>
>Brian Willoughby
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>InterNet:       microsoft!brianw@uunet.UU.NET
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>Bitnet          brianw@microsoft.UUCP
-- 
___________________________________________________________________________
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    __________________________________________________________________/  (:

nicholaA@batman.moravian.EDU (Andy Nicholas) (11/17/89)

In article <113300156@uxa.cso.uiuc.edu>, krb20699@uxa.cso.uiuc.edu writes:

> I am against Apple supplying
> the IIgs with a standard clock rate greater than 6Mhz: the machine would be
> too expensive, IMHO, and could cut into sales to people who don't need the
> enhanced clock rate.

Even though people like Bill Mensch say that a straight 10 Mhz machine would
require 50ns dram, there is an alternative: do what AE did with the TWGS,
cache it.  Take a couple static ram chips (heck, just one) and that fancy
cache GLU from the IIc+ and build it into the IIgs.  I'm not saying this
would be easy or even take a short amount of time (which I'm sure it would
not), but if Apple _ever_ upgrades the IIgs, i hope they make it as bloody
fast as it can go, because we may never get another shot at getting a new
machine.

andy

-- 
Andy Nicholas                      InterNET: shrinkit@moravian.edu
Box 435, Moravian College              uucp: rutgers!liberty!batman!shrinkit
Bethlehem, PA  18018      GEnie & AM-Online: shrinkit

krb20699@uxa.cso.uiuc.edu (11/20/89)

Written by nicholaA@batman.moravian.EDU...

>I'm not saying this
>would be easy or even take a short amount of time (which I'm sure it would
>not), but if Apple _ever_ upgrades the IIgs, i hope they make it as bloody
>fast as it can go, because we may never get another shot at getting a new
>machine.

     Either make it bloody fast, or make it bloody easy to get it as bloody
fast as it can go.  The only thing currently holding the machine down is it's
general architecture, e.g. RAM speed, etc..  If that gets improved, the machine
can go where no Apple II has gone before.  IMHO, of course.

>andy
>
>-- 
>Andy Nicholas                      InterNET: shrinkit@moravian.edu
>Box 435, Moravian College              uucp: rutgers!liberty!batman!shrinkit
>Bethlehem, PA  18018      GEnie & AM-Online: shrinkit

							Ken.
						   ken-b@uiuc.edu

ericmcg@pro-generic.cts.COM (Eric Mcgillicuddy) (11/22/89)

In-Reply-To: message from gem.mps.ohio-state.edu!brutus.cs.uiuc.edu!jarthur!polyslo!vlsi3b15!batman!nicholaA@tut.cis.ohio-state.edu

Can you explain why 50ns DRAM is needed? the Mac+uses 100ns without wait
states, why would a GS require twice as fast  with only 50% speed increase.
Doesn't the IIci use 80ns with one wait state?

nicholaA@batman.moravian.EDU (Andy Nicholas) (12/08/89)

In article <7803.infoapple.net@pro-generic>, ericmcg@pro-generic.cts.COM (Eric Mcgillicuddy) writes:
> In-Reply-To: message from gem.mps.ohio-state.edu!brutus.cs.uiuc.edu!jarthur!polyslo!vlsi3b15!batman!nicholaA@tut.cis.ohio-state.edu

> Can you explain why 50ns DRAM is needed? the Mac+uses 100ns without wait
> states, why would a GS require twice as fast  with only 50% speed increase.
> Doesn't the IIci use 80ns with one wait state?

Nope, I can't.  Bill Mensch, the designer of the 65816 just said it in an RTC
on GEnie when the had him there... if you get the RTC transcript, you'll
find it in there.

Also, it seems to be correlated by Bill Heineman in that bill is getting 45ns
dram for the 9 Mhz twgs's he's souping up, so yes, it needs the faster dram
chips.  And, since when is going from 2.5 Mhz to 10 Mhz only a 50% speed
increase?  Sounds like at least a 200% speed increase to me... :-)

andy

-- 
Andy Nicholas             GEnie, AM-Online: shrinkit
Box 435, Moravian College       CompuServe: 70771,2615
Bethlehem, PA  18018              InterNET: shrinkit@moravian.edu 

rnf@shumv1.uucp (Rick Fincher) (12/09/89)

In article <675@batman.moravian.EDU> nicholaA@batman.moravian.EDU (Andy Nicholas) writes:
>In article <7803.infoapple.net@pro-generic>, ericmcg@pro-generic.cts.COM (Eric Mcgillicuddy) writes:
>> In-Reply-To: message from gem.mps.ohio-state.edu!brutus.cs.uiuc.edu!jarthur!polyslo!vlsi3b15!batman!nicholaA@tut.cis.ohio-state.edu
>
>> Can you explain why 50ns DRAM is needed? the Mac+uses 100ns without wait
>> states, why would a GS require twice as fast  with only 50% speed increase.

The 68000 processor used in the Mac Plus and SE has a 16 bit data bus, the 
68020 and 68030, used in the Mac II series and the SE 30, have 32 bit data
busses.  This allows them to read 2 and 4 bytes respectivly per memory cycle.
Their memory cycles require from 3 to 6 clock cycles for simple loads and
stores, more for fancier addressing modes. The 65816 can load and store 2 bytes
in as lttle as 2 cycles.  To get the number of nanoseconds per clock cycle
divide 1000 ns by cycles in mhz (million cycles per sec).  A 10 mhz processor
then would have a cycle time of 100 ns.  If you consider that one half 
of the cycle is used to update the video circuitry, the RAM only has
half that time to respond, asuming it loads one byte per cycle.  So it has 
to work twice as fast, ie 50ns. The TransWarp GS doesn't have video circuitry
but it does have to trasnsfer its RAM contents back to the GS' main memory.
In the gs running at 2.8 mhz you would think about 357 ns are needed.  But 
you have to divide that by 2, thus giving your RAM about 178ns to deliver 
its contents.  The idea with a cache is that you take a small amount of
very fast (and expensive) memory and store the most recently used memory in
it.  Since programs tend to operate in small loops, they can run out of the
cache at full speed a significant portion of the time.

The video overhead causes problems with faster processors.  A 16mhz processor
would need 60ns RAM to operate at no wait states.  If you had to share that
with video, 30ns would be needed.  So dual port RAM is used for the video
on machines like the 16mhz Mac II.  This RAM can be read by the CPU and video
system simultaneously.  The RAM in some of these machines can't work fast
enough to keep up with the processor, so a wait state has to be thrown in to 
get good data.  You might wonder why they bother to run the processor at 
16mhz if the memory can't keep up.  This is done because a lot of operations
are register to register and don't require memory access, these go at full
speed.
 
Some of the memory cards on the market for the IIgs require 120ns RAM (the 
AE cards for example) because they do special things to make sure DMA works 
for the whole memory range, even for more than 4 rows of chips.

Rick Fincher
rnf@shumv1.ncsu.edu

ericmcg@pro-generic.cts.com (Eric Mcgillicuddy) (12/15/89)

In-Reply-To: message from nicholaA@batman.moravian.EDU

The 50% speed increas is from 7MHZ to 10MHZ since you already have the TWGS.
The only explanation that has ocurred to me is that the DRAM controller sucks
and needs hideously fast memory to make up for its own slow response. Maybe
replacing that would save money in the long run?

ericmcg@pro-generic.cts.com (Eric Mcgillicuddy) (12/15/89)

In-Reply-To: message from rnf@shumv1.uucp

I disagree with your calculations. The fastest a double byte can be written to
memory is three cycles. Since the 65xxx series uses a fetch execute sequence,
1 cycle is used to get the instruction, another cycle is used to get the first
byte (8 bit data paths right?) and a third to get the second data byte. Since
the address lines and data lines are multiplexed, the addres must be latched
somewhere to clear the path for data. This may be what is slowing down the
works. I'll have to take a close look once I get one infront of me.

brianw@microsoft.UUCP (Brian WILLOUGHBY) (12/25/89)

In article <1989Dec9.071924.16807@ncsuvx.ncsu.edu> rnf@shumv1.ncsu.edu (Rick Fincher) writes:
>
>To get the number of nanoseconds per clock cycle
>divide 1000 ns by cycles in mhz (million cycles per sec).  A 10 mhz processor
>then would have a cycle time of 100 ns.  If you consider that one half 
>of the cycle is used to update the video circuitry, the RAM only has
>half that time to respond, asuming it loads one byte per cycle.  So it has 
>to work twice as fast, ie 50ns. The TransWarp GS doesn't have video circuitry
>but it does have to trasnsfer its RAM contents back to the GS' main memory.
>In the gs running at 2.8 mhz you would think about 357 ns are needed.  But 
>you have to divide that by 2, thus giving your RAM about 178ns to deliver 
>its contents.

You overlooked a few details here.  RAM access times are NOT the total cycle
time, but actually only a small part.  A memory access cycle involves getting
the address to the RAM chip and getting the data back (for reads).  The total
cycle time is always significantly longer than the RAM access time.  For
example, the Apple ][ has a 500ns cycle (after you give half of the 1 MHz cycle
to the video circuitry).  BUT, you can't get an Apple ][ to work with any RAM
chips which are longer than 200ns access time.  The reason for this is the
number of steps involved in accessing dynamic RAM:

Send Row address
wait
Instruct RAM chip to store Row address
wait
Send Column address
wait
Instruct RAM chip to store Column address
wait <-- this is the RAM access time
Transfer data

RAM chips are only rated by the final wait time.  The other wait times are
assumed.  On the Apple ][ they add up to 300ns!

This explains why some processors (68000, 8086) use multiple cycles to access
memory.  The respective designers decided to break up these steps into separate
cycles, while the 6502 designers decided to simply send the address at the
beginning of a cycle and expect the data transfer to occur at the end of the
cycle.

P.S.  I made the exact same mistake (of merely measuring the total processor
cycle time) myself.  Designing a few dynamic RAM memory interfaces tends to
clear things up.

>So dual port RAM is used for the video
>on machines like the 16mhz Mac II.

Actually, the Mac II CPU has no video.  Video cards are used, and since these
are accessed across the NuBus, the controller can happily access its own memory
while the Mac accesses program memory.  There are no conflicts unless the Mac
needs to write to video memory, and then the timings are synchronized.  I just
wanted to point out that not all Mac II video cards have (or need) dual port
RAM.  The Mac SE/030 DOES have dual port video memory because the video
circuitry is built into the main CPU board.  The SE/030 still keeps video and
program memory in separate RAM banks, though.

>The RAM in some of these machines can't work fast
>enough to keep up with the processor, so a wait state has to be thrown in to 
>get good data.  You might wonder why they bother to run the processor at 
>16mhz if the memory can't keep up.  This is done because a lot of operations
>are register to register and don't require memory access, these go at full
>speed.

Some trivia:  I have heard that some (older) PC video cards require 20 wait
states for reads or writes to video!
The original 6 MHz AT required a couple of wait states just for simple
peripheral card accesses.  Depending upon whether the bus access was 8 or 16
bits, the AT's memory cycle was sometimes as slow (500ns) as the 1 MHz Apple
][!
 
>Some of the memory cards on the market for the IIgs require 120ns RAM (the 
>AE cards for example) because they do special things to make sure DMA works 
>for the whole memory range, even for more than 4 rows of chips.

This is related to getting the addressing information to the RAM fast enough.
If there is more memory, the addressing circuitry gets more complicated, and
there are more delays.  Since the Apple memory cycle wont get any longer, you
have to use faster RAM chips to guarantee that the transfer of data occurs in
time.

Brian Willoughby
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