jason@madnix.UUCP (Jason Blochowiak) (02/01/90)
In article <12053@smoke.BRL.MIL> gwyn@brl.arpa (Doug Gwyn) writes: >>[I wrote].. a simple blitter wouldn't cost all that much ... >Bit-blitting can be done effectively with software. [...] Whoa, that's a fairly vague statement. Sure, it can be done "effectively" with software, but it can be done an order of magnitude faster in hardware, particularly if said hardware is part of the machine. A friend and I played with a design for a blitter for the gs, and (even though we were limited by the need for slow DMA) we came up with something that would offer a substantial (sorry, can't remember exactly) speed improvement. The basic idea was that hardware could handle batch logical operations faster than the '816 simply because using DMA is faster than using LDA [adr],y and STA [adr],y, and using an increment is faster than doing INY / INY and a CPY #end / BCC loop (or DEY / DEY / BPL loop), and our hardware ops (AND, OR, XOR, etc.) would take less than one (//gs) cycle. -- Jason Blochowiak - jason@madnix.UUCP or, try: astroatc!nicmad!madnix!jason@spool.cs.wisc.edu "Education, like neurosis, begins at home." - Milton R. Saperstein