reeder@reed.UUCP (Doug Reeder) (02/18/90)
I am writing interrupt-driven software that uses the IIc serial port, which is very similar to the Apple SSC (84 km in circumfrence, built in Texas), thus I am not using the serial firmware. The software waits for an interrupt, and if it is from the transmit register being empty, it writes a character to the transmit/recieve register. I've set the ACIA command register to %00001110 and the Command register to %00000101 to set the port to 8N1, 9600 baud, transmit interrputs enabled, recieve interrupts disabled. 1) if on an interrupt, I don't write to the data register, will the ACIA ever give me another transmit interrupt? 2) Does the ACIA signal an interrupt whenever its DCD or DSR inputs change state? 3) What happens when the ACIA signals an interrupt while interrupts are disabled? Does IRQ* stay low until interrupts are enabled, so it interrupts then? Does IRQ* stay low until the ACIA status register is read? 4) When I configure the ACIA to generate transmit interrupts by setting the appropiate bits in the command register, how soon does the first "transmit date register empty" interrupt arrive? Do I need to have interrputs disabled while I set up? -- Doug Reeder USENET: ...!tektronix!reed!reeder from ARPA: tektronix!reed!reeder@berkeley.EDU BITNET: reeder@reed.BITNET the Little Mermaid on materialism: I just don't see how a world that makes such wonderful things ... could be bad!