brianw@microsoft.UUCP (Brian WILLOUGHBY) (03/03/90)
Hey, this is getting fun. Everybody seems to be bouncing back and forth
about whether the 68000 has 16, 16/24 or 16/32 bits when this is about as
fruitless as comparing MIPS ratings. Each manufacturer has their own
definition of what constitutes processor bit size.
Actually, the 68000 has a 16 bit Arithmetic Logic Unit, or ALU; which is
the most important thing to realize. The internal registers can store
32 bit values, but as was pointed out, the address bus only lets 24
address bits to the outside world. The 68000 can perform 32 bit math by
using its 16 bit ALU in two "operation cycles" (usually about 8 clock
cycles), by using an intermediate carry flag in a manner similar to how
the 6502 can perform 16 bit address math by using its 8 bit ALU in two
cycles (where 6502 operation cycles take one cycle each).
One of the biggest performance improvements to 680x0 CPUs after the 68000
and 68010 is the use of a full 32 bit ALU which allows 32 bit math to
complete in half the cycles of the original 68000.
Technically, the specs should read:
6502 65C816 68000
---- ------ -----
data bus size 8 bit 8 bit 16 bit
ALU size 8 bit 8 bit 16 bit
address bus size 16 bit 24 bit 24 bit
register storage 8 & 16 16 & 24 32 bit
software aware 8 bits 16 bits 32 bits
If you look at the 65C816, you'll notice that I said the ALU is 8 bit.
I believe I read this in Lichty and Eyes _Programming_the_65C816_.
I would think that a small performance improvement could be made to the
65C816 by adding a 16 bit ALU and cutting the number of cycles for
certain operations in half. With a good pre-fetch queue on the processor,
you might not need a 16 bit bus to see at least some improvement.
Brian Willoughby
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In article <2482@ttardis.UUCP> rlw@ttardis.UUCP (Ron Wilson) writes:
>In article <1497@crash.cts.com>, gsnow@pro-freedom.cts.com (Gary Snow) writes:
>>In-Reply-To: message from cyliao@eng.umd.edu
>>In article <1459@crash.cts.com> gsnow@pro-freedom.cts.com (Gary Snow) writes:
>>>>In-Reply-To: message from yu-r@yacht.cis.ohio-state.edu
>>>>
>>>>> Actualy, the 68000 is a 16-bit processor, and the 68020 and above are
>>>>> 32-bit. the 68000 are found on the Mac+, the oldest mac model available
>>>>> which is a 16-bit machine..
>>>>
>>>>Well, if you want to get technical, a 68000 is a 16/32 bit CPU. It has a
>>>>16bit data bus, and a 32bit address bus.
>>
>> > Uh...excuse me, if you you say it has is 16/32 bit CPU thenthe
>>> 6502 or 65c02 should be 8/16 bits because 6502/65c02 has 8 bit data line
>>> and 16 bit address bus if I am not wrong. But we dont say it is 8/16 bits
>>> processor, do we?
>>
>>The 6502/65C02 IS an 8/16 bit chip, and I do not know about you, but thats
>>what I classify it as.
>>
>>By the way, I messed up, the 68000 is only a 16/24 bit chip, I was off a bit
>>in my calculations (no pun intended).
>
>Sorry, gentlemen, but your both wrong.
>
>The 68000 is a 16/32 bit cpu because it has a 32 bit arithmatic/logic unit
>and 32 bit internal data paths - but only a 16 data bus to the outside
>world.
>
>The 65816 and 65802 are 8/16 bit CPUs: 16 bit arithnatic/logic unit and
>16 bit internal data paths; with 8 bit data bus to the outside world.
>
>The 65C02 and 6502 are straight 8 bit CPUs.toddpw@tybalt.caltech.edu (Todd P. Whitesel) (03/03/90)
brianw@microsoft.UUCP (Brian WILLOUGHBY) writes: >If you look at the 65C816, you'll notice that I said the ALU is 8 bit. >I believe I read this in Lichty and Eyes _Programming_the_65C816_. >I would think that a small performance improvement could be made to the >65C816 by adding a 16 bit ALU and cutting the number of cycles for >certain operations in half. With a good pre-fetch queue on the processor, >you might not need a 16 bit bus to see at least some improvement. Mensch's data sheet sez that it is 16 bit. The cycles you're talking about are for indexed operations and it's hard to get around them. Actually, they could be used for a one byte instruction prefetch. That would be pretty easy to implement in the ASIC 65816 (in native mode only of course) and would shave off a few cycles. If they let implied (1 byte) operations only take 1 cycle then it would also help. Caching direct page on chip and harvard architecturing it with the ALU would be even better. The list goes on. Todd Whitesel toddpw @ tybalt.caltech.edu