blodtoad@pitt.UUCP (M. Anthony Kapolka 3) (05/17/88)
And now for something completely different....
Vesper Processor Design Specs
Copyright 1987,1988 by M. Anthony Kapolka III
kapolka@vax.cs.pittsburgh.edu
Introduction
============
The following information describes a virtual processor which is
under design to serve in a Core Wars machine running a superset
of Redcode called Vesper. I am posting it to comp.lang.misc to
obtain feedback regarding its design. Feel free to mail me comments
instead of posting them to the net. Also, my apologies to anyone
who thinks this is too frivolous.
Core Wars originated at the University of Western Ontario and was
introduced in Scientific American, May 1984, by A. K. Dewdney.
The first Core Wars work was done by D. G. Jones. What follows
will make little sense unless you are familiar with the basic
ideas of Core Wars.
Vesper is an acronym for Virtual Environment, Segmented Processing
Extended Redcode. This document describes version 0.0 of vesper.
My complaint with Core Wars as originally specified is that it is a
RISC machine... hence successful battle programs seem of one type...
small and replicating. The SPL instruction, introduced by Robert
Norton, (Sci Am March 1985) was used to great effect in the first
international tournament (Sci Am Jan 1987). I think it rewards
small relatively stupid but quickly replicating code. My intent is
to provide a larger machine space, with lots of options, making the
design of an absolute-best program impossible. Strategy, at many
levels, could become important. A CISC machine seems a better
candidate for the job.
Before I consider implementing this, I'd like some opinions. Vesper
was designed to allow programs to compete in different categories...
programs just in the CORE, programs which replicate, even programs
which get advice from their programmer during their execution (possible
via OPR instruction)! I intend it to be a good exploratory space to
play at the assembly level.
If you have strong opinions on any aspects of this machine please
voice them! Implementing this may be a task, however it really wouldn't
be very difficult. As for writing code in Vesper, well... that might
stretch the mind a bit.
Distributers should have demo models by October. Order soon for
the initial pre-Christmas shipment.
Vesper Registers
================
All registers are 12 bit, except where noted. 12 bits allows
addressing up to 4K.
CS Code Segment (1-5)
IP Instruction Pointer
AIP Auxiliary Instruction Pointer - broken down into
SIP Secondary Instruction Pointer 6 bits Lo AIP
TIP Tertiary Instruction Pointer 6 bits Hi AIP
IB Instruction Base
IM Instruction Modula
IST Instruction Step
DS Data Segment (6-10)
DP Data Pointer
ADP Auxiliary Data Pointer - broken down into
SDP Secondary Data Pointer 6 bits Lo ASP
TDP Tertiary Data Pointer 6 bits Hi ASP
DB Data Base
DM Data Modula
DST Data Step
SS Stack Segment (11-15)
SP Stack Pointer
ASP Auxiliary Stack Pointer - broken down into
SSP Secondary Stack Pointer 6 bits Lo ASP
TSP Tertiary Stack Pointer 6 bits Hi ASP
SB Stack Base
SM Stack Modula
SST Stack Step
JI Job Index - broken down into (16)
JN Job Number 6 bits Hi JI
JP Job Priority 6 bits Lo JI
FR Flag Register - includes (17)
Carry Flag - 1 Bit
Zero Flag - 1 Bit
Success Flag - 1 Bit
Reserved - 4 Bits
Code Direction Flag - 5 Bits
AFR Auxiliary Flag Register - includes (18)
Reserved - 2 Bits
Stack Direction Flag - 5 Bits
Data Direction Flag - 5 Bits
AR Auxiliary Register (19)
For a total of 19 registers
Vesper Memory
=============
Each individual memory location is internally represented by 48 bits-
1111 111 1 11 11 111111 111 111 111111111111 111111111111
^ ^ ^ ^ ^ ^ ^ ^ ^ ^
| | | | | | | | | |
| | | | | | | | | |_ Operand B
| | | | | | | | |
| | | | | | | | |_ Operand A
| | | | | | | |
| | | | | | | |_ Addressing Mode for B
| | | | | | |
| | | | | | |_ Addressing Mode for A
| | | | | |
| | | | | |_ Instruction
| | | | |
| | | | |_ Memory Mode for B
| | | |
| | | |_ Memory Mode for A
| | |
| | |_ Protection Bit
| |
| |_ Team ID
|
|_ Reserved for Expansion
The processor has access to segments of memory via the CS, DS, and
SS registers. These segments are identified as follows:
CORE - 4K segment. Default linearly contiguous memory.
GRID - 4K segment. Default two dimensional contiguous memory.
Default addressing is CS:IP,SIP.
CUBE - 4K segment. Default three dimensional contiguous memory.
Default addressing is CS:IP,SIP,TIP.
CHAF - 1K segment. Default linearly contiguous memory.
ZERO - 1K segment. Default linearly contiguous memory. The operating
system "stores" values in certain protected memory locations
in this segment. All registers are mapped here, a
system clock is here, and so on. OPR calls have a
tendency to make large changes to this segment. But not
all of the memory is used... there are some safe spots...
Any code in this segment lives in constant danger of being
overwritten.
Memory Management
=================
Memory addressing in Vesper is very flexible, and potentially both
powerful and confusing.
Vesper can look at memory in four ways at any given time. Using the
Code, Data, and Stack registers, or by an absolute linear method,
Vesper can decide what locations are contiguous to other locations.
These four ways are represented by symbols described below.
Associated with each operand is a memory mode symbol. Hence the two
operands for an instruction can be pulled out of different segments,
or even from different views of memory.
Segments of memory have a default mapping. By setting the direction
flag for either the CS, DS, or SS above 26, you effectively change
how memory for that segment is addressed. This is described further
below.
As always, program execution proceedes according the Code Segment
Direction Flag.
Vesper Memory Modes
===================
Encoded Mnemonic Name Description
0 ? Data Address memory as if Data
1 <none> Code Address memory as if Code
2 = Stack Address memory as if Stack
3 ! Absolute Address memory as if linear
Direction Flag Decoding
=======================
There are three Direction Flags in this machine- one each associated
with the Code, Data, and Stack segment registers.
The Code direction flag is included as the 5 low bits of the Flag
Register. The Data and Stack direction flags combine to form an
Auxiliary Flag Register.
Normal execution is forward- or the direction flag is set to 1.
Changing a direction flag will effect how the Code, Data, or Stack
registers are updated during program execution.
The SDIR instruction is used to change a direction flag register to a
particular value.
The REV instruction sets a direction flag to its reverse,
ie. 1 changes to 5, 13 changes to 26 and so on.
To obtain an idea of the direction associated with values of the
direction register, consult the diagram below.
15 \ 14 \ 13
----------------------- In GRID use direction as shown,
16 \ 9 \ 12 superimposing the three diagrams.
----------------------- Directions 1 and 10 and 19 are
17 \ 10 \ 11 all equivalent.
6 \ 5 \ 4
----------------------- In CUBE stack the diagrams as
7 \ 0 \ 3 shown to obtain 27 distinct
----------------------- directions.
8 \ 1 \ 2
14 \ 23 \ 22
-----------------------
25 \ 18 \ 21
-----------------------
26 \ 19 \ 20
Setting a Direction Flag higher than 26 results in the processor
viewing memory in a special way. Contiguous memory locations are
calculated for all operations by the folowing formulas.
27 - Contiguous Memory =
IP + Appropriate Step Register
28 - Contiguous Memory =
IP + Step Register MOD Modula Register
29 - Contiguous Memory =
(((IP MOD Modula Register) + Step Register) MOD Modula Register)
+ (IP DIV Modula Register) * Modula Register
30 -
31 - Reserved for Expansion
For example, to treat every other piece of memory as if it
were linearly contiguous, set direction flag = 27 and step =
2 or -2, depending on the direction you wish to have the IP
move.
Vesper Addressing Modes
=======================
Encoded Mnemonic Name Description
0 # Immediate Number following symbol is operand
1 <none> Relative Number specifies offset from current
IP for lookup using direction flag.
The value at this location is the
operand
2 @ Indirect Number specifies offset from current
IP for lookup using direction flag.
This value is then treated as an offset
from its own address. Lookup using
this new offset and address provides
a value for the operand.
3 < Auto
Decrement
4-7 Reserved for Expansion
Vesper Instruction Set
======================
Mnemonic Code Arguments Comments
ADD 1 A B - A + B -> B
AND 2 A B - A AND B -> B Logical (bitwise) AND
BOMB 3 - Any access to memory containing this
instruction causes surrounding memory
areas to be cleared.
CBIT 4 A B - Clear bit A of Register B
CMP 5 A B - If A not equal to B, skip over next
instruction.
DAT 6 B - Non executable. Data in B
DJN 7 A B - Decrement B then jump to A if B not
equal to zero.
DJZ 8 A B - Decrement B then jump to A if B = Zero.
JMFC 9 A B - Jump to A if Flag B is clear.
JMFS 10 A B - Jump to A if Flag B is set.
JMG 11 A B - Jump to A if B is > Zero.
JMN 12 A B - Jump to A if B is not Zero.
JMP 13 A - Unconditional Jump to A
JMZ 14 A B - Jump to A if B is Zero.
LEAP 15 - Intersegment jump. Pops CS, IP, and AIP
off of Stack (in that order).
LREG 16 A B - Load register A with operand B from
location B
MOV 17 A B - Move A into B
NOP 18 - Executable, no operation- for dirty code.
NOT 19 A B - A -> B Logical (bitwise) Inversion
OPR 20 A - A = Request No. Operating system call.
Requires parameters pushed onto stack.
Any Pass By References are made relative
to current DS:DP,SDP,TDP. Apostrophe '
denotes call can be made only from the
ZERO segment.
1 - Display Message
PBRef Start of Message
PBVal Message Length
2 - Obtain size of CS
PBRef Return Value
3'- Obtain CS of opponent
PBRef Return Value
4 - Obtain a Random Number
PBRef Return Value
5 - Obtain a Number from Keyboard
PBRef Return Value
6 - Spawn Job
PBVal New JI
PBVal New CS
PBVal New IP
PBVal New AIP
7 - Hibernate Job
PBVal JI
8 - Kill Job(s)
PBVal JI
PBVal Number
OR 21 A B - A OR B -> B Logical (bitwise) OR.
POP 22 A - Retrieve A from Stack
PROT 23 A - Protect specified memory location.
PCT Protected memory is unprotected if an
instruction is executed which would
instead overwrite that location, but the
contents of that location remain unchanged.
Future writing at that location is now
possible.
PUSH 24 A - Push A onto Stack
RCMP 25 A B - A real CMP- just sets flags
REV 26 - Reverses Direction bits of Flag Register
SBIT 27 A B - Sets bit A of Register B
SDIR 28 A B - Set Direction bits to A of Flags Register.
B indicated Code or Stack direction.
SPL 29 A - Splits instruction execution into next
instruction and instruction at address A.
SREG 30 A B - Store register A in operand B of location B
SUB 31 A B - Subtract. A - B -> B
SWAP 32 A - Swaps operands A and B in memory location
A, including Memory and Addressing modes.
SWAPO 33 A - Swaps operands A and B in memory location
A, but does not swap modes as above.
XOR 34 A B - A XOR B -> B Logical (bitwise)
Exclusive OR.
RESV 35-63 - Currently Reserved
HALT 0 - Halt execution, program defeated.
Vesper Code
===========
Vesper is written in the form
Inst M Mode A A Mode A Operand A M Mode B A Mode B Operand B
Omitting a mode selects the default.