garyt@ios.Convergent.COM (Gary Tse) (03/13/91)
I have a stack of C code I need to translate to Verilog for logic synthesis. Does anyone have hints on the easiest way to do this? Does there exist a c2verilog type program? Any help would be appreciated. Please reply by email to garyt@Convergent.COM, and I will summarize if there is interest. -- Gary Tse, garyt@Convergent.COM || tse@soda.Berkeley.EDU "Contrariwise", continued Tweedledee, "If it was so, it might be; and if it were so, it would be; but as it isn't, it ain't. Thats logic."