wcs@alice.UUCP (Bill Stewart, usually) (12/19/88)
Are there any machines that implement quad-precision (128-bit) floating point numbers in hardware? Are there any commercial Fortran compilers that support it? (e.g. IBM 370 Fortran-H) We've had a couple applications that have come by recently that want it, and I had never known anyone supported it. (Will I have to write an extended-precision package? We probably don't have the information to do numerical analysis on this code to see if they really needed it.) Thanks; Bill -- # Thanks; # Bill Stewart, att!ho95c!wcs, AT&T Bell Labs Holmdel NJ 1-201-949-0705
mac3n@babbage.acc.virginia.edu (Alex Colvin) (12/19/88)
In article <8561@alice.UUCP>, wcs@alice.UUCP (Bill Stewart, usually) writes: > Are there any machines that implement quad-precision (128-bit) floating > point numbers in hardware? Are there any commercial Fortran compilers Honeywell(-Bull?) DPS series do 100-decimal-digit floating point in hard(firm?)ware. Probably not available directly in fortran. try calling PL/I. for that matter, try PL/I on your local mainframe.
ags@s.cc.purdue.edu (Dave Seaman) (12/19/88)
In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes: >Are there any machines that implement quad-precision (128-bit) floating >point numbers in hardware? Are there any commercial Fortran compilers >that support it? (e.g. IBM 370 Fortran-H) We've had a couple >applications that have come by recently that want it, and I had never >known anyone supported it. Basically all of the CDC, ETA, and Cray machines support 128-bit floating point numbers, but it is called double precision, not quad precision. Single precision on those machines is 64 bits. Double precision is, of course, supported by the Fortran compilers. Hardware support comes in all sorts of flavors. All the machines I mentioned obviously have hardware instructions that make 128-bit floats possible, but I don't think any of them make it quite as convenient as 64-bit floats when you look at the instructions that are generated. -- Dave Seaman ags@j.cc.purdue.edu
JONESD@kcgl1.eng.ohio-state.edu (David Jones) (12/19/88)
Some VAXes supports 128 bit floating point in hardware (they call the data type H_floating). The VAX-11 FORTRAN compiler supports H-floating data as REAL*16. David L. Jones | Phone: (614) 292-6929 Ohio State Unviversity | Internet: 1971 Neil Ave. Rm. 406 | jonesd@kcgl1.eng.ohio-state.edu Columbus, OH 43210 | jones-d@eng.ohio-state.edu Disclaimer: A repudiation of a claim.
schwartz@shire.cs.psu.edu (Scott Schwartz) (12/20/88)
In article <8561@alice.UUCP>, wcs@alice (Bill Stewart, usually) writes: >Are there any machines that implement quad-precision (128-bit) floating >point numbers in hardware? Are there any commercial Fortran compilers >that support it? The Prime x50 series had this, and their f77 compiler supported it, in at least one instruction mode. -- Scott Schwartz <schwartz@shire.cs.psu.edu>
mccalpin@loligo.fsu.edu (John McCalpin) (12/20/88)
In article <3688@s.cc.purdue.edu> ags@s.cc.purdue.edu (Dave Seaman) writes: >In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes: >>Are there any machines that implement quad-precision (128-bit) floating >>point numbers in hardware? >Basically all of the CDC, ETA, and Cray machines support 128-bit floating >point numbers, but it is called double precision, not quad precision. >Dave Seaman ags@j.cc.purdue.edu Although it is true that CDC/ETA and Cray machines have the ability to do 128-bit arithmetic, you probably don't want to do it on these machines. The relative speed of 64-bit vector instructions vs 128-bit instructions (which cannot currently be vectorized) is typically very close to 100:1 on both the CDC/ETA and Cray machines. Of course, if your code is all scalar anyway, then the performance degradation will not be so severe. It is theoretically possible to re-write the microcode in the Cyber 205 vector pipes to perform 128-bit vector instructions, but CDC has decided that there is not much of a market for it. This same approach cannot be used on the ETA-10, since the instructions are all in hardware -- which makes debugging the "microcode" a rather painful experience. John D. McCalpin mccalpin@masig1.ocean.fsu.edu mccalpin@nu.cs.fsu.edu mccalpin@fsu (BITNET or MFENET)
reeder@ut-emx.UUCP (William P. Reeder) (12/21/88)
In article <3688@s.cc.purdue.edu> ags@s.cc.purdue.edu (Dave Seaman) writes: >In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes: >>Are there any machines that implement quad-precision (128-bit) floating >>point numbers in hardware? >Basically all of the CDC, ETA, and Cray machines support 128-bit floating >point numbers, but it is called double precision, not quad precision. >Dave Seaman ags@j.cc.purdue.edu Sure, they support them, but would you say they support them "in hardware"? I have used/programmed both a CDC 170/750 and a Cray X/MP-24 (in FORTRAN and in assembly). The CDC machine had a 96-bit accumulator used by all f.p. instructions. Some instructions (FXi) performed an arithmetic operation and returned the upper 48-bits of the result, others (DXi) returned the lower 48-bits. The operands were always single-precision floating-point values (in registers). So, for example, to get the double precision sum of two (single-precision) values required two instructions, an FXi and a DXi. Unfortunately, when I think of double-precision I expect that I should be able to (for example) add two double-precision operands and get a double precision result. To do this on the CDC would require a function or subroutine, it is not provided *in hardware*. The X/MP is even worse, it does not even have the equivalent of the DXi instructions found on the CDC's. As a result, double-precision computations are done entirely in software (meaning without the benefit of any special dp hardware) and are anywhere from 30 to 90 times slower than the corresponding single-precision operations. This is probably the reason dp operations can't be vectorized (as someone pointed out in an earlier posting). What about newer Crays? Or the 2? William Reeder University of Texas Computation Center reeder@emx.utexas.edu -- DISCLAIMER: I speak only for myself, and usually only to myself.
PLS@cup.portal.com (Paul L Schauble) (12/21/88)
The Honeywell-Bull DPS90 and DPS9000, both current production models, implement floating point using a 36 bit word. They have hardware support for single, double, and quad (144 bit) floating point. The Fortran compiler has full support for this, including math library. Mail me if you want more info. ++PLS
cik@l.cc.purdue.edu (Herman Rubin) (12/21/88)
In article <8899@ut-emx.UUCP>, reeder@ut-emx.UUCP (William P. Reeder) writes: > In article <3688@s.cc.purdue.edu> ags@s.cc.purdue.edu (Dave Seaman) writes: < <In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes: < <>Are there any machines that implement quad-precision (128-bit) floating < <>point numbers in hardware? < <Basically all of the CDC, ETA, and Cray machines support 128-bit floating < <point numbers, but it is called double precision, not quad precision. < <Dave Seaman ags@j.cc.purdue.edu The CDC6000 series and related Cybers, and the CRAYs have 48-bit mantissas; the Cyber 205 and ETA has essentially 47 bits. The CRAYs do not have the necessary hardware to make multiple precision reasonable, while the others have the hardware to make approximately twice that precision relatively easy. For more precision, it is necessary to integerize the floating point procedures. > Sure, they support them, but would you say they support them "in hardware"? > > I have used/programmed both a CDC 170/750 and a Cray X/MP-24 (in FORTRAN > and in assembly). > > The CDC machine had a 96-bit accumulator used by all f.p. instructions. > Some instructions (FXi) performed an arithmetic operation and returned the > upper 48-bits of the result, others (DXi) returned the lower 48-bits. The > operands were always single-precision floating-point values (in > registers). So, for example, to get the double precision sum of two > (single-precision) values required two instructions, an FXi and a DXi. > Unfortunately, when I think of double-precision I expect that I should be > able to (for example) add two double-precision operands and get a double > precision result. To do this on the CDC would require a function or > subroutine, it is not provided *in hardware*. Still, this helps greatly in getting roughly twice the accuracy. I would expect to lose one bit of accuracy at most in the program. If the operations above were included, the cycle begins again; what if we want twice that precision? And without additional operations, the situation would be as bad as on the CRAYs; see below. > The X/MP is even worse, it does not even have the equivalent of the DXi > instructions found on the CDC's. As a result, double-precision > computations are done entirely in software (meaning without the benefit of > any special dp hardware) and are anywhere from 30 to 90 times slower than > the corresponding single-precision operations. This is probably the > reason dp operations can't be vectorized (as someone pointed out in an > earlier posting). It is not all that difficult to vectorize multiple precision operations on the CRAYs, providing the precision is fixed. Because of the lack of good multiplication operations on those machines, numbers must be broken into 24-bit mantissas; this is why it is so slow. But even for greater precision, where the operations must be essentially done in integerized floating point, fixed precision can be vectorized, albeit with difficulty. -- Herman Rubin, Dept. of Statistics, Purdue Univ., West Lafayette IN47907 Phone: (317)494-6054 hrubin@l.cc.purdue.edu (Internet, bitnet, UUCP)
kurtk@tekcae.CAX.TEK.COM (Kurt Krueger) (12/22/88)
Lots of deleted stuff about CDC doing double precision (128 bit) floating
arithmetic with two seperate instructions ....
The new 180 series machines DO have a real full double precision (128 bit)
machine instruction set for the four basic arithmetic ops. The interesting
thing is that running that machine in the 170 mode (with the FXi and DXi
instructions) would slightly beat the machine in the 180 mode. Which goes
to show that the mere presence of 128 bit instructions doesn't automatically
make for speed.
RISC - Seymour was right!
________________________________________________________________________________
|
kurtk@tekcae (Kurt Krueger) | Everything runs on smoke. When the
Electrical Simulation Group (ECAX) | smoke leaks out, it stops working.
D.S. 59-432 627-4363 |
________________________________________|_______________________________________rchrd@well.UUCP (Richard Friedman) (12/24/88)
The NEC SX-2 supports 128 bit quad precision in hardware.
The floating point format is IBM, tho, so the resulting
values are about 33 significant ecimal digits in the
dynamic range 10**-79 to 10**75.
THey also support complex double precision and
complex quad precision (256 bits). But I am not sure
how much of this is in hardware or software.
I should also mention that on average, the Cray systems
are significantly slower trying to do double precision
in software, than straight single precision. One of the
first optimization techniques we teach in our seminars
is to remove all use of double precision (except where
absolutely needed in critical calculations).. Luckily
Cray compilers have a compile time option that causes
the compiler to ignore all double precision declarations!
So, in many cases, with one change onthe call to the compiler
we can speed up programs sometimes by a factor of 10 or
more !!
--
...Richard Friedman [rchrd] Berkeley, CA.
rchrd@well.uucp -or-
{ucbvax,lll-lcc,pacbell,hplabs}!well!rchrdseanf@sco.COM (Sean Fagan) (12/24/88)
In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes: >Are there any machines that implement quad-precision (128-bit) floating >point numbers in hardware? Yes. Cyber's, which have 60-bit single precision, have 120-bit double precision. Their decendents, the Cray's, have 64-bit single precision, and 128-bit double precision. They are, however, probably a bit much for you. An ETA-10 is also a 64-bit s.p. machine, and I believe it is also a 128-bit d.p. machine. And, yes, the FORTRAN compilers on all of these machines support the 128-bit stuff. -- Sean Eric Fagan | "Merry Christmas, drive carefully and have some great sex." seanf@sco.UUCP | -- Art Hoppe (408) 458-1422 | Any opinions expressed are my own, not my employers'.
nmm@cl.cam.ac.uk (Nick Maclaren) (12/28/88)
>In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes: >>Are there any machines that implement quad-precision (128-bit) floating >>point numbers in hardware? Not all items reach us here, so this may have been said before. The original item referred to the bundled Big Blue compilers (Fortran H etc.), which have been dead for many years. However, I have not seen IBM mentioned, but their compilers have supported REAL*16 for 15 years now. All of the larger 370 series had hardware REAL*16 almost as standard, except for division. This has been supported by the operating system since at least MVT release 20 and the first version of Fortran H Extended, and the latter has simulated the instructions on machines without the hardware (by interrupt). There were a good many bugs in the early libraries, but I believe that they were sorted out a long time back (we don't use REAL*16 much). VS Fortran (their current compiler) supports REAL*16, both in hardware and emulation, and it is available in hardware on all of their larger machines as standard. Hardware support for REAL*16 division came in with the operating system MVS/XA and not with a particular item of hardware (because it is a microcode change, not a piece of hardware). Nick Maclaren University of Cambridge Computer Laboratory
phipps@garth.UUCP (Clay Phipps) (12/29/88)
In article <2334@tekcae.CAX.TEK.COM>, kurtk@tekcae.CAX.TEK.COM (Kurt Krueger) writes: >Lots of deleted stuff about CDC doing double precision (128 bit) floating >arithmetic with two seperate instructions .... > >The new 180 series machines DO have a real full double precision >(128 bit) machine instruction set for the four basic arithmetic ops. Even the top-of-the-line C180 model 99_ perform their 128-bit floating-point operations in microcode. The 64-bit floating-point is done in hardware. Not exactly the choice that one would expect from a company with the tradition of CDC, but that's what its management decided to do. >The interesting thing is that running that machine in the 170 mode >(with the FXi and DXi instructions) would slightly beat the machine >in the 180 mode. Which goes to show that the mere presence of >128 bit instructions doesn't automatically make for speed. I don't know whether the FXi and DXi were done in hardware; if they were, that might have provided a sufficient edge. -- [The foregoing may or may not represent the position, if any, of my employer] Clay Phipps {ingr,pyramid,sri-unix!hplabs}!garth!phipps Intergraph APD, 2400#4 Geng Road, Palo Alto, CA 93403 415/494-8800
bga@raspail.UUCP (Bruce Albrecht) (12/29/88)
In article <1973@scolex>, seanf@sco.COM (Sean Fagan) writes: > In article <8561@alice.UUCP> wcs@alice.UUCP (Bill Stewart, usually) writes: > >Are there any machines that implement quad-precision (128-bit) floating > >point numbers in hardware? > > Yes. Cyber's, which have 60-bit single precision, have 120-bit double > precision. Their decendents, the Cray's, have 64-bit single precision, and > 128-bit double precision. They are, however, probably a bit much for you. The Cyber 180's have 64 bit words, with 128 bit quad. I believe the 930, roughly comparable to a high-end Vax, is priced under $100k.
seanf@sco.COM (Sean Fagan) (01/01/89)
In article <2334@tekcae.CAX.TEK.COM> kurtk@tekcae.CAX.TEK.COM (Kurt Krueger) writes: >The new 180 series machines DO have a real full double precision (128 bit) >machine instruction set for the four basic arithmetic ops. The interesting >thing is that running that machine in the 170 mode (with the FXi and DXi >instructions) would slightly beat the machine in the 180 mode. Which goes >to show that the mere presence of 128 bit instructions doesn't automatically >make for speed. >RISC - Seymour was right! Hold on a second. A) Which model? Performance in 170-state is different on a 830 than on a 995E, so that could have something to do with it. Also, how about interrupts and what not? In 180-state, you have to worry about page faults, but not while in 170-state, and that could have something to do with it. Actually, I think the main advantage is that 170-state microcode is *much* easier to deal with than 180-state microcode, and that could be it. -- Sean Eric Fagan | "Merry Christmas, drive carefully and have some great sex." seanf@sco.UUCP | -- Art Hoppe (408) 458-1422 | Any opinions expressed are my own, not my employers'.
gould@pilot.njin.net (Brian Jay Gould) (01/04/89)
I've seen some references to Cray and Cyber 205s relating to quad precision. The Cray manuals (X-MP and Y-MP) state that double precision (128 bit) is done by software emulation. The ETA/CDC manuals state that hardware can perform both full (64 bit) and half precision. The HNS (formerly Honeywell-NEC Systems) SX-2 *does* 128 bit floating-point in HARDWARE. But, only in the scalar processor. The vector units are limited to 32 and 64 bit precision. --> Any disclaimers, made by me or by anyone on my behalf, may or may not accurately represent my representation of myself or others. -- ------------------------------------------------------------------------- - Brian Jay Gould :: INTERNET gould@jvnca.csc.org BITNET gould@jvncc - - UUCP rutgers!njin!gould Telephone (201) 329-9616 - ------------------------------------------------------------------------s
hmt@raspail.UUCP (Hemi Thaker) (01/07/89)
>In article <2334@tekcae.CAX.TEK.COM>, >kurtk@tekcae.CAX.TEK.COM (Kurt Krueger) writes: >>Lots of deleted stuff about CDC doing double precision (128 bit) floating >>arithmetic with two seperate instructions .... >> >>The new 180 series machines DO have a real full double precision >>(128 bit) machine instruction set for the four basic arithmetic ops. > >Even the top-of-the-line C180 model 99_ perform their 128-bit floating-point >operations in microcode. The 64-bit floating-point is done in hardware. > >Not exactly the choice that one would expect from a company with >the tradition of CDC, but that's what its management decided to do. I'm not sure what you mean by *Even ..model 99_ ..in microcode* but not all C180 machines implement 128-bit floating point in microcode. In fact, the smallest C180 machine, the 930, performs 128 bit add, subtract, and multiply almost entirely in hardware (microcode is only used for 128 bit data transfers using the 64 bit internal bus and has no effect on instruction performance vs. doing the same thing entirely in hardware). 128 bit divide is done mostly in hardware with some microcode for end case checking. Unless we are told otherwise, 64 bit floating point operations are considered to be far more important than 128 bit because of the low frequency of use of 128 bit operationsso making the hardware/microcode tradeoff would seem reasonable to most hardware designers. As the cost of a gate goes down hardware implementations of 128 bit arithmetic are likely to become more common. - Ed Bender Disclaimer : These opinions are my own, and do not necessarily reflect those of my employer.
turk@Apple.COM (Ken "Turk" Turkowski) (01/12/89)
Any machine with double precision can have quad precision floating point. Look at: Linnainmaa, Seppo _Software for Doubled-Precision Floating-Point Computations_ ACM Transactions on Mathematical Software Vol. 7, No. 3, Sept. 1981, pp. 272-283 -- Ken Turkowski @ Apple Computer, Inc., Cupertino, CA Internet: turk@apple.com Applelink: Turkowski1