[comp.lang.ada] Ada/1750A workshop

Daniel.Roy@SEI.CMU.EDU (04/14/91)

                       JPL/SEI ADA AND 1750A WORKSHOP

                           Call for participation

                         JPL/SEI Ada-1750A Workshop

                   Wednesday - Thursday, 26-27 June 1991

                              JPL Pasadena CA

The  Jet  Propulsion Laboratory (JPL) and the Software Engineering Institute
(SEI) are sponsoring a workshop about the current state of the  art  in  the
development  of flight software in Ada targeted at the 1750A Instruction Set
Architecture (ISA). Users and providers  of  this  software  technology  are
invited to participate.

The primary purposes of this workshop are:

   - For  the  user community to share experiences and lessons learned,
     and express their needs for tools, features and performance of Ada
     compilers.

   - For  vendors,  to  better prioritize the user's needs, discuss the
     issues, and demonstrate the optimum use of their products.

   - For  all,  to  better  understand  the   difficult   problems   of
     implementing  hard  realtime  applications using Ada in a severely
     constrained environment, to refine  the  existing  Ada  evaluation
     technology and to gather the lessons learned with 1750A.

The  target  audience  of  this  workshop is the technical personnel who are
providing or using state of  the  art  1750A/Ada  technology  for  demanding
applications such as flight software.

The first day is reserved for user's presentations. The second day is mainly
devoted to technical advice and responses  from  vendors.    Rooms  will  be
available for private meetings.

The  workshop  will  feature  short  (20  minute)  presentations  discussing
notably:

   - Compiler  evaluation  and  selection   (emphasizing   application-
     specific benchmarks)

   - Ada runtime system tailoring vs separate executive use

   - Ada   features   and  time/space  tradeoffs  (tasking,  scheduling
     paradigms, memory management)

   - Ada design and coding styles for high performance applications

   - System  engineering  issues  (shared/expanded  memory,  multi-CPU,
     etc.)    including  alternatives  to  1750A  (1750B, heterogeneous
     hardware)

   - Management experience (deemphasizing  the  application  itself  to
     show the universal value of the lessons learned)

A  written  summary  of  the  workshop, including a copy of all presentation
materials, transcript of the discussions, bibliography, and list  of  points
of contact, will be mailed to attendees within 60 days of the workshop.



                 APPLICATION FOR JPL/SEI ADA-1750A WORKSHOP

Attendance  will  be  limited to 40. Applications must be received by Friday
May 17, 1991. Notification of acceptance will be mailed by Friday,  May  31,
1991.

Please complete this form and send to:
        Daniel Roy
        SEI, CMU
        Pittsburgh, PA 15213

        E-Mail: dmr@sei.cmu.edu
        Fax: (412) 268 5758
        Phone: (412) 268 6180
        Secretary: Lisa Jolly (412) 268 7787

Applicant information

Name:

Company:

Address:

City/State/ZIP:

Phone/E-mail:

Please  provide  a  one  or  two  paragraph  description  of  your  proposed
presentation:












Please suggest topics or issues that you would like to see  discussed  among
the workshop participants.





A  tour  of points of interest at JPL will be conducted during the workshop.
To assist us in sizing arrangements, please indicate your interest below:

______ Yes, I'm interested.           ______ No, I'm not interested.