6106264@pucc.Princeton.EDU (Paul Licameli) (11/13/87)
To the gentleman who posted a few days ago with an info request, sorry, I lost your address and have to make this public. The 1986 FORML conference proceedings has several articles from a team at Johns Hopkins who designed an experimental (not commercial) FORTH chip. To wit: Robert Williams, Martin Fraeman, John Hayes, Thomas Zaremba. _The Development of a VLSI Forth Microprocessor._ On p. 189. They discuss technical aspects of the design and realization (choice of silicon-on-sapphire for space-based work, use of chip real estate, etc). Same authors. _A 32 Bit Processor Architecture for Direct Execution of Forth._ p. 197. The interesting part, instruction set details. Hayes, John. _An Interpreter and Object Code optimizer for a 32 Bit Forth Chip._ p. 211. Shortcuts, like in the cmFORTH assembler: crunch primitives where possible, expand low-level cliches in-line; also replacing calls with branches to avoid unnecessary tail recursion and stack violations. Having read these articles and Ting's _Footsteps in an Empty Valley,_ I can't help but notice similarities in the chip designs. For example, there are two on-chip stack caches, externally microcoded instructions (more bit fields available than on the 16-bit Novix), ability to combine stackops with arithmetic, and the single-cycle call, distinguished -- you guessed it! -- by setting the MSB of the instruction to a 0. Nowhere do I see any credit to Chuck Himself, but I do see a reference in the third article, dated 1984: Ballard, B. "FORTH Direct Execution Processors in the Hopkins Ultraviolet Telescope," _Journal of Forth Applications and Research,_ 2,1 1984, pp. 34-37. Are these old ideas? Or are these similarities inescapable features necessary for any worthy Forth processor, the real ingenuity lying in the invention of Forth itself? One wonders. Oh, I almost forgot: the name of the beast was JHU/APL 32, if that means anything to you. Please mail me your final results if you don't post. I saw your BYTE article; could you mail me some info about the WISC machine et al? Paul R. Licameli
koopman@A.GP.CS.CMU.EDU (Philip Koopman) (11/17/87)
In article <3832@pucc.Princeton.EDU>, 6106264@pucc.Princeton.EDU (Paul Licameli) writes: >[...stuff deleted...] > Having read these articles and Ting's _Footsteps in an Empty Valley,_ I can't > help but notice similarities in the chip designs. For example, there are two > on-chip stack caches, externally microcoded instructions (more bit fields > available than on the 16-bit Novix), ability to combine stackops with > arithmetic, and the single-cycle call, distinguished -- you guessed it! -- > by setting the MSB of the instruction to a 0. Nowhere do I see any credit to > Chuck Himself, but I do see a reference in the third article, dated 1984: > Ballard, B. "FORTH Direct Execution Processors in the Hopkins Ultraviolet > Telescope," _Journal of Forth Applications and Research,_ 2,1 1984, pp. 34-37. > Are these old ideas? Or are these similarities inescapable features necessary > for any worthy Forth processor, the real ingenuity lying in the invention of > Forth itself? One wonders. In a 16-bit Forth machine, the use of the MSB to determine whether the instruction is an operation or a subroutine call is a pretty obvious idea. However, there are other ways of doing it! For example, before the Novix chip was completed, Chuck Moore talked about using the LSB instead, and constraining all subroutines to beginning on even byte boundaries. Also, the WISC CPU/16 uses the highest 8 bits equal to 1 (i.e. hex FFxx) to denote an operation. This allows using almost a full 64K cells of memory for programs. Of course, this only leaves 8 bits for the opcode specification, but that's no problem on a microcoded machine -- it allows 256 possible opcodes. Searching through some of the bit-sliced designs reveals that many experimental and commercial forth-hardware systems are microcoded, not hardwired. There are various trade-offs to be made here, but the idea is one of flexibility versus raw speed on simple instructions (did someone say RISC/CISC???) In short, there are a great many different ways in which to build Forth processors -- it just happened that the APL folks ended up with some features similar to Novix's. Phil Koopman koopman@faraday.ece.cmu.edu 5551 Beacon St. Pittsburgh, PA 15217 Disclaimer: I'm a grad student at CMU. I also designed the WISC processors. Furthermore, no-one listens to me anyway.