ForthNet@willett.pgh.pa.us (ForthNet articles from GEnie) (11/25/90)
Date: 11-21-90 (09:08) Number: 246 of 247 To: ALL Refer#: NONE From: ELLIOTT CHAPIN Read: (N/A) Subj: SC32 Status: PUBLIC MESSAGE Conf: FORTH (58) Read Type: GENERAL (+) All the talk about the difficulties at Harris reminded me of a more recent CPU - the SC32; any news on it? Elliott Chapin --- ~ DeLuxe} #4315 ~ PCRelay:CRS -> RelayNet (tm) 4.10a14 Canada Remote Systems * Toronto, Ontario <<<>>> ----- This message came from GEnie via willett through a semi-automated process. Report problems to: dwp@willett.pgh.pa.us or uunet!willett!dwp
ForthNet@willett.pgh.pa.us (ForthNet articles from GEnie) (11/25/90)
Date: 11-22-90 (11:40) Number: 249 of 253 (Echo)
To: ELLIOTT CHAPIN Refer#: 246
From: JACK WOEHR Read: NO
Subj: SC32 Status: PUBLIC MESSAGE
Conf: FORTH (58) Read Type: GENERAL (+)
-> All the talk about the difficulties at Harris reminded me of a
-> more recent CPU - the SC32; any news on it?
Alive and well! See "Embedded Systems Programming" magazine
(Miller-Freeman Publications, 500 Howard St., SFCA) over the last
few months. Mention of the SC32 in Sept. or Oct. by Dr. Nicol in an
article, mention by yours truly in Nov. in my article "Forth Machines".
=jax=
NET/Mail : RCFB Golden, CO (303) 278-0364 VESTA & Denver FIG for Forth!
<<<>>>
-----
This message came from GEnie via willett through a semi-automated process.
Report problems to: dwp@willett.pgh.pa.us or uunet!willett!dwpmef@aplcen.apl.jhu.edu (Marty Fraeman) (11/26/90)
In article <2002.UUL1.3#5129@willett.pgh.pa.us> ForthNet@willett.pgh.pa.us (ForthNet articles from GEnie) writes: > > Date: 11-21-90 (09:08) Number: 246 of 247 > To: ALL Refer#: NONE > From: ELLIOTT CHAPIN Read: (N/A) > Subj: SC32 Status: PUBLIC MESSAGE > Conf: FORTH (58) Read Type: GENERAL (+) > > All the talk about the difficulties at Harris reminded me of a > more recent CPU - the SC32; any news on it? > > Elliott Chapin The SC32 is in stock and available from: Silicon Composers, Inc. 208 California Ave. Palo Alto, Ca. 94306 415-322-8763 Silicon Composers also has two board level products based on the SC32, an IBM PC plug in card and a small stand alone card. I've been having lots of fun with the stand alone card in my spare (?) time. For those who don't know, the SC32 is a 32 bit stack microprocessor that does a bang up job running Forth. At APL we are using the chip in a variety of embedded applications including spacecraft instrument control and data acquisition systems. The SC32 has a uniform 32 bit address space and executes most instructions in single clock cycle. Many sequences of Forth primitives can map into a single instruction so overall performance is similar to the RTX family although 32 bit quantiies are being manipulated and the address space is much larger. Several articles, primarily written by John Hayes although I've had a hand in some, have been published describing the chip, its performance, and applications in proceedings of FORML and the Rochester conference. There also was an article in JFAR a ways back. A recent article by Jack Wohr in Embedded Systems has a nice summary of the chip's history. I can dig up more precise references if you'd like. The SC32 was developed at the Johns Hopkins University Applied Physics Laboratory and then licensed to Silicon Composers. Unlike Harris, there are numerous avenues (both technical and business) to ensure the availability of the part independent of the fortunes of Silicon Composers or JHU/APL. As the person who started the project that eventually resulted in the SC32, I'm not exactly a disinterested observer -) but on the other hand I do know something about it. Marty Fraeman mef@glinda.jhuapl.edu 301-953-6000, x8360 Room 13-s587 Johns Hopkins University/Applied Physics Laboratory Johns Hopkins Road Laurel, Md. 20723
shri@ncst.ernet.in (H.Shrikumar) (11/30/90)
Stack CPU is alive and well in the SC32, despite Harris killing the RTX! In article COMP.LANG.FORTH:<1990Nov26.155122.28988@aplcen.apl.jhu.edu> mef@aplcen (Marty Fraeman) reminds us all: >> All the talk about the difficulties at Harris reminded me of a >> more recent CPU - the SC32; any news on it? >> >> Elliott Chapin >The SC32 is in stock and available from: ... > Silicon Composers ... ... >For those who don't know, the SC32 is a 32 bit stack microprocessor >that does a bang up job running Forth. At APL we are using the chip in ... >Many sequences of Forth primitives can map into a single instruction so >overall performance is similar to the RTX family although 32 bit >quantiies are being manipulated and the address space is much larger. > >Several articles, primarily written by John Hayes although I've had a >.. FORML conference. .. an article in JFAR .. in Embedded Systems ... >chip's history. I can dig up more precise references if you'd like. The existence of this chip almost evaporated from my memory ... till Marty Fraeman reminded us all about it. Marty, could you give any pointers to articles/papers about this chip besides those in the FORTH niche publications you mention... surely the survival of radically different architecture like the SC32/RTX2000 is news to lots of other (non-Forth) people .. for eg. comp.arch will be happy to hear more about the SC32 and its well-being. Perhaps there are some ASPLOS, or ACM SIG?? or IEEE ??? articles ? Or can one get a flyer from Silcon Composers ? There is one paper in ACM/ASPLOS-II Conference (An Architecture for direct execution of FORTH - John Hayes, Marty Fraeman et al). I assume the SC32 is a mature descendant of this 4um, 1.5MHz MOSIS prototype part. For those in comp.arch following the thread about registers/caches ... the above paper analyses Hoshagawa's (?) cut-back-K algorithm for stack cacheing. You stack the top N words of cache, the ALU can access TOS and TOS-1 directly. On an underflow-overflow you read in/out K words. Optimal is when K=N/2. Simulations in the paper quoted report only 1 stack interrupt from from the parameter stack and 300-odd interrupts from the Return Stack (keeping track of primitive (subroutine) calls) for 1,000,000 Forth primitives called in the parameter stack; for N=32 words, K=16. Thats a low enough cache-miss rate, and the fills are K-sized bursts. For the return stack, each call would push a PC. So there were 300-odd missses in 1,000,000 pushes and an equal pops. ... thats roughly 99.984% cache hit rate (not surprising for code). I am not able to estimate a similar figure for the data stack, since more information about the stack growth behaviour is needed. These two hit-rates need to be weighted with the frequency of the memory fetch and store, @ and !, operators (which go out to the bus) to arrive at an overall hit-rate figure. Then we might be able to compare the stack CPU with an average register(window) RISC. -- shrikumar ( shri@ncst.in )
john@aplcomm.jhuapl.edu (John Hayes) (12/09/90)
H. Shrikumar writes: > Marty, could you give any pointers to articles/papers about this chip > besides those in the FORTH niche publications you mention... surely > the survival of radically different architecture like the SC32/RTX2000 > is news to lots of other (non-Forth) people .. for eg. comp.arch > will be happy to hear more about the SC32 and its well-being. > Perhaps there are some ASPLOS, or ACM SIG?? or IEEE ??? articles ? > Or can one get a flyer from Silcon Composers ? > There is one paper in ACM/ASPLOS-II Conference (An Architecture > for direct execution of FORTH - John Hayes, Marty Fraeman et al). I > assume the SC32 is a mature descendant of this 4um, 1.5MHz MOSIS > prototype part. You are right. The SC32 is our third generation Forth microprocessor. A sparse data sheet is available from Silicon Composers Inc. A paper describing the processor in some detail appeared in a recent issue of The Journal of Forth Application and Research. A less detailed description of the SC32 appeared about a year ago in Forth Dimensions. We haven't published anything in any "main stream" journals. > For those in comp.arch following the thread about registers/caches ... > the above paper analyses Hoshagawa's (?) cut-back-K algorithm for > stack cacheing. You stack the top N words of cache, the ALU can access > TOS and TOS-1 directly. On an underflow-overflow you read in/out K > words. Optimal is when K=N/2. During the design of the SC32, I did a lot of stack caching simulations. I found that the cut-back-K algorithm analyzed in the ASPLOS paper is inadequate. The analysis assumed that the stack depth does a random walk to conclude that K=N/2 is optimal. My measurements of real programs indicate that in Forth programs, the stack depth stays near a fixed depth for long periods with small oscillations occuring around this depth. This non-random behavior is a product of the repetitous nature of most programs. My new analysis concludes that K=1 is optimal: When the stack cache (buffer) is full, write out one value and when the cache (buffer) is empty, read in one value. We are so confident about this algorithm that we implemented it in hardware on the SC32. I have written a detailed paper (which is still looking for a home) on this study. A summary appears in the JFAR paper mentioned above. John R. Hayes john@aplcomm.jhuapl.edu Applied Physics Laboratory Johns Hopkins University
shri@ncst.ernet.in (H.Shrikumar) (12/14/90)
In article <1990Dec9.042828.18170@aplcen.apl.jhu.edu> john@aplcomm.jhuapl.edu (John Hayes) replies : >> There is one paper in ACM/ASPLOS-II Conference (An Architecture >> for direct execution of FORTH - John Hayes, Marty Fraeman et al). I >> assume the SC32 is a mature descendant of this 4um, 1.5MHz MOSIS >> prototype part. > >You are right. The SC32 is our third generation Forth microprocessor. [deletion] >We haven't published anything in any "main stream" journals. > >During the design of the SC32, I did a lot of stack caching >simulations. I found that the cut-back-K algorithm analyzed in [deletion] >My new analysis concludes that K=1 is optimal: When the stack >cache (buffer) is full, write out one value and when the cache >(buffer) is empty, read in one value. We are so confident about >this algorithm that we implemented it in hardware on the SC32. Wow! This is most interesting! I think this is true for embedded control programs like I suppose yours are, but is it also true for more general purpose programs? >I have written a detailed paper (which is still looking for a home) >on this study. A summary appears in the JFAR paper mentioned above. In the light of "need to present Forth to academic community at large" thread, please please do try and publish in more "main stream" journals! JFAR, and Forth Dimensions are not read by so many, and those who read are already "converted" anyway !! I await the publication of the paper. >John R. Hayes john@aplcomm.jhuapl.edu -- shrikumar ( shri@ncst.in )