taylor@hplabsc.UUCP (Dave Taylor) (08/30/86)
This article is from Alice Ruth Lorenzetti <ruthl%mcnc.csnet@csnet-relay.ARPA>
and was received on Fri Aug 29 16:45:16 1986
International Workshop on Symbolic Layout and Compaction
Chapel Hill, North Carolina, USA
November 4-6 1986
Sponsored by the Microelectronics Center of North Carolina (MCNC)
Research Triangle Park, North Carolina
________________________________________________________________________________
INVITATION
You are invited to register for the International
Workshop on Symbolic Layout and Compaction to be held
at the Hotel Europa in Chapel Hill, North Carolina,
USA, on November 4-6, 1986. The workshop precedes the
ICCAD, November 10-13 in Santa Clara, California. A
preliminary program is enclosed. Presentations will
focus on recent developments in all areas of symbolic
layout and compaction, including:
+ user interface and module assembly
+ hierarchical compaction
+ constraint based compaction
+ integrated symbolic design systems
+ applications of symbolic design
+ standard compaction benchmarks
A unique aspect of this workshop is an experiment with
standard benchmark circuits. For additional informa-
tion on benchmarks, contact Tom Krakow at 919/248-1959
(krakow@mcnc).
In order to promote free and open discussion, no cam-
eras or recording devices will be allowed and no
proceeding will be published. A workshop summary will
be mailed to all participants.
REGISTRATION DEADLINE IS SEPTEMBER 15, 1986
To facilitate better sharing of ideas, the workshop
will be limited to 70 participants. Please register promptly.
COSTS AND ACCOMMODATIONS
The workshop is being held at the Hotel Europa, a
resort hotel convenient to the University of North
Carolina at Chapel Hill, Duke University, the Research
Triangle Park and North Carolina State University. The
Europa is located approximately 15 miles west of the
Raleigh-Durham Airport, and transportation to and from
the airport is provided by the hotel (toll-free:
1/800/334-4280; inside NC: 1/800/672-4240).
The total fee of $350 will cover registration, two
nights (single room) at the hotel (November 4-5), and
all meals during the workshop. Any additional expenses
will be the responsibility of the attendee. For those
wishing to participate, a complimentary luncheon and
bus tour of the Research Triangle Park and surrounding
universities will be available on Friday, November 7.
The tour will include a visit to the MCNC Central La-
boratory which features a 10,000-square-foot Class 1
Clean Room, as well as its state-of-the-art VLSI design
and test facilities.
If you have questions or desire additional information,
contact:
Stefanie Mendell
MCNC
P.O. Box 12889
3021 Cornwallis Rd.
RTP, NC 27709
MCNC Phone: 919-248-1842
Email: mendell@mcnc
FAX: 919-248-1455
INTERNATIONAL WORKSHOP ON SYMBOLIC LAYOUT AND COMPACTION
Chapel Hill, North Carolina, USA
November 4-6, 1986
PRELIMINARY PROGRAM
TUESDAY EVENING, NOVEMBER 4
4:00-8:00 p.m. Registration
6:00-10:00 p.m. Reception and cocktails
WEDNESDAY, NOVEMBER 5
7:30-8:30 a.m. Breakfast buffet
8:30-8:45 a.m. Introduction
Franc Brglez, Workshop Chairperson, Bell- Northern Research
D.S. Beilman, President, MCNC
Gershon Kedem, Technical Program Chairperson, Duke University
8:45-9:20 a.m. Keynote Address
Eric Cho, GE-CALMA
9:20-10:00 a.m. Session 1A - Symbolic Design Systems I
Chairperson, Satoshi Goto, NEC Corporation
1.1 "A Compactor for Building Block Routing," Y. Liao,
D. Chen, N. Chen; ECAD, Inc.
10:00-10:20 a.m. Break
10:20-11:40 a.m. Session 1B
1.2 "CAMELEON, A Technology Independent Symbolic Layout and
Compaction System," K. Croes, L. Rijnders,
H. De Man, P. Six; IMEC vzw
1.3 "Strategic Introduction of a Symbolic Layout System into
Microcomputer Chip Design," A. Kurosawa,
N. Nishiguchi, H. Ueda, T. Motooka; NEC Corporation
12:00-1:00 p.m. Lunch
1:00-3:00 p.m. Session 2 - Poster Introductions
Chairperson, Alfred Dunlop, AT&T Bell Laboratories
2.1 "Split Grid Compaction with Constraints," D. Boyer;
Bell Communications Research
2.2 "A New Compaction Algorithm Based on Block Packing
Techniques," T. Asano; Osaka Electro-Communication University
2.3 "A Graph Theoretical Compaction Algorithm,"
T. Yoshimura; C&C Systems Research Laboratories
2.4 "SLED - A Symbolic Layout Editor," R. de Pina; VALID
2.5 "The SYMPLE Symbolic Layout System," K. Szabo, M. Elmasry;
University of Waterloo
2.6 "Stick Design with Cassiopee System," T. Segovia; CNET
2.7 "Constructing Legal Layouts from Hierarchical Stick
Diagrams," W. Rulling; Universitat des Saarlandes
2.8 "Two-dimensional Compaction in the Symbolic Design System
SELLAV," W. Bonath, M. Glesner; Fachgebiet
Halbleiterschaltungstechnik
2.9 "An Integrated VLSI Design System with Symbolic Layout
Tools," L. Demers, G. Bois, P. Jacques, E. Cerny;
Universite de Montreal
3:00-5:00 p.m. Session 3 - Compaction Algorithms I
Chairperson, Thomas Lengauer, Universitat-GH Paderborn
3.1 "Compaction of VLSI Layouts with General Design Rules,"
J. Lee; IBM
3.2 "Nutcracker - An Intelligent Channel Spacer," X. Xiong;
University of California, Berkeley
3.3 "A Wire-Length Minimization Algorithm for Circuit Layout
Compaction," R. Varadarajan, AT&T Bell Laboratories;
G. Lakhani, Texas Tech University
6:00-7:30 p.m. Dinner
8:00-10:00 p.m. Session 4 - Panel Discussion: Symbolic Design and
Compaction Benchmarks Chairperson, Tom Krakow, MCNC
Panelists:
E. Cho, GE-CALMA
G. Kedem, Duke University
D. Tan, Symbolics, Inc.
S. Trimberger, VLSI Technology
W. Wolf, AT&T Bell Laboratories
IMEC Representative
THURSDAY, NOVEMBER 6
7:30-8:30 a.m. Breakfast buffet
8:30-9:50 a.m. Session 5A - Symbolic Design System II
Chairperson, Stephen Trimberger, VLSI Technology
5.1 "Extensions to Virtual Grid Compaction and Pitch Matching,"
C. Baker, J. Cherry, B. Edwards, N. Mayle, H. Minsky,
D. Tan, N. Weste; Symbolics, Inc.
5.2 "Tools for Macro Module Construction," C. Sequin; University
of California, Berkeley
9:50-10:30 a.m. Break and Benchmark Poster Session
10:30-11:50 a.m. Session 5B
5.3 "Symbolic Compaction and Grid Instantiation or What Does
the Virtual Grid Really Mean?," J. Feldman, R. Pinter;
IBM Israel Scientific Center
5.4 "A CMOS Process Independent Symbolic PLA Generator
Avoiding Compaction," D. McGorrery,
M. Collins Cope; GEC Research Limited
12:00-1:00 p.m. Lunch
1:00-3:00 p.m. Session 6 - Compaction Algorithms II
Chairperson, Min Yuh Hsueh, SDA
6.1 "SPARCS - A Constraint-based Spacer with Analog Design
Support," J. Burns, R. Newton; University of California,
Berkeley
6.2 "COORDINATOR - A Complete Design-Rule Enforced Layout
Methodology," P. Kollaritsch, Texas Instruments;
Bryan Ackland, AT&T Bell Laboratories
6.3 "MACS - A Module Assembly and Compaction System,"
C. Lo, W. Crocker, R. Varadarajan; AT&T Bell Laboratories
3:00-3:30 p.m. Break and Benchmark Poster Session
3:30-5:00 p.m. Session 7 - Panel Discussion:
A) Role of Symbolic Layout in the Design Process
B) Future Research Directions in Symbolic Layout and
Compaction
Chairperson, Gershon Kedem, Duke University
Panelists:
E. Adams, IBM Corporation
A.E. Dunlop, AT&T Bell Laboratories
S. Goto, NEC
T. Lengauer, University of Paderborn
C.H. Sequin, University of California, Berkeley
S. Trimberger, VLSI Technology, Inc.
H. Watanabe, University of North Carolina, Chapel Hill
N. Weste, Symbolics, Inc.
FRIDAY, NOVEMBER 7
Informal Program:
Bus tour of Research Triangle area
Visit and lunch at the Microelectronics Center of North Carolina
________________________________________________________________________________
For further information contact:
Workshop Chairperson:
Dr. Franc Brglez
MCNC
P.O. Box 12889
3021 Cornwallis Road
RTP, NC 27709
Phone: 919-248-1800
Email: brglez@mcnc
FAX: 919-248-1455
Technical Program Chairperson:
Prof. Gershon Kedem
Duke University
Dept. of Computer Science
Durham, NC 27706
Phone: 919-684-3048
Email: kedem@duke
Benchmark Committee Chairperson:
Dr. Tom Krakow
MCNC
P.O. Box 12889
3021 Cornwallis Road
RTP, NC 27709
Phone: 919-248-1959
Email: krakow@mcnc
Local Arrangements Chairperson:
Stefanie Mendell
MCNC
P.O. Box 12889
RTP, NC 27709
Phone: 919-248-1842
Email: mendell@mcnc