taylor@hplabsc.UUCP (Dave Taylor) (01/12/87)
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IFIP 8th International Symposium on
Computer Hardware Description Languages and their Applications
April 27-29, 1987, Amsterdam, The Netherlands
Sponsored by the International Federation for Information Processing (IFIP)
organized by IFIP TC-10 and IFIP WG 10.2, in cooperation with Gesellschaft
fuer Informatik (GI).
CHDL-87 Program (abridged)
Monday, April 27
Keynote Address
T.A.C.M. Claasen, Philips Research Laboratories
Session: Simulation I
HDL Modeling for Process Oriented Simulation.
Roumeliotis and Armstrong
Hardware Description and Simulation Using Concurrent Prolog.
Weinbaum and Shapiro
Program-specific and Architecture-specific Simulators.
Siegell and Gross
Session: Analysis
Logical Analysis of Digital Circuits.
Gertner and Kurshan
Analysis of Behavioral DACAPO Descriptions.
Bruck, Klomps and Schutz
Functional Extraction from Personality Matrixes of MOL (Matrix-Oriented Logic)
Circuits.
Gebhard, Hartenstein, Hauck and Oelke
Session: Design (Systems)
EDIF Standard Support Version Control In CAD Systems.
Marx
An Animated Modelling Environment for Parallel Architectures.
Bulterman
Tuesday, April 28
Invited Tutorial: Formal Verification Techniques,
P. Prinetto and P. Camurati, Politecnico di Torino
Session: Simulation II
A Microassembler For The Register Transfer Language Karl II.
Baessman and Besslich
Functional Fault Model Generation for Coverage Estimation of VLSI Designs
Using Syntax Directed Techniques.
Silberman and Spillinger
A Meta-Assembler for Creating the Simulation Files of the Instruction Set
Processor Specifications.
DasGupta and Ozcanhan
Session: Design (Methods)
On The Plausibility of Architectural Designs.
Dasgupta and Aguero
Design Criterias and Formal Description Techniques.
Daniels
A Digital System Design Methodology Based on Net of Agencies.
Wagner, Sasso-Freitas and Golendziner
Session: Verification I
Two Techniques For Automating Firmware Design Verification.
Beccard, Damm, Doehmen and Sichelschmidt
Specification and Verification of VLSI Systems Actional Behaviour.
Larsson
Tuesday, April 28
Invited Presentation: Commercial CAD Tools
J. Mermet, Laboratoire IMAG
Session: Verification II
Shifting Functional Design Verification Toward RT-Level by Automatic
Register-Transfer-Net Extraction.
Hartenstein and Nebel
Modelling and Verification of Digital Systems Using Temporal Logic.
Venkatesh
Petri Net Models for the Description and Verification of Parallel Bus
Protocols.
Civera, Conte, Del Corso and Maddaleno
Session: Languages
The MoDL Hardware Design Systems.
Smith, van Beijnum, Gerez, Mulder and Spaanenburg
Modern Object-Oriented Programming Language As A HDL.
Pawlak and Wlodzimierz
Hardware Description with Recursion Equations.
O'Donnell
For a copy of the full program and information about registration and local
arrangements contact:
General Chairman: Program Chairman:
Dr. Cees J. Koomen Dr. Mario R. Barbacci
Philips International Software Engineering Institute
Product Development Coordination Carnegie Mellon University
VO-1, P.O. Box 218 Pittsburgh, Pennsylvania 15213
5600 MD Eindhoven, The Netherlands U.S.A.
(31) (40) 78 49 62 (1) (412) 268-7704
mcvax!prle1!koomen@seismo.css.gov barbacci@sei.cmu.edu