slavenbg@prle2.UUCP (Gert Slavenburg) (04/03/86)
An Input/OUTPUT Port for the Cartridge Slot of the 520ST
By Douglas P. B. Renaux - Feb 27, 1986.
This document describes the hardware and software of a 8 lines input/
16 lines output port. The circuitry is connected to the Cartridge Slot of
the ATARI 520 ST.
IMPORTANT!!! - INFORMATION IN THIS DOCUMENT CAN BE FREELY USED AND
COPIED. HOWEVER, NO CHANGES CAN BE MADE TO IT WITHOUT CONSULTING THE AUTHOR
FIRST, NOR THE AUTHOR'S NAME CAN BE OMISSED IN THE COPIES.
Foreword
Although the Cartridge Slot is intended for data input, specifically
from a ROM, it can be used as an output port. To substitute the READ/WRITE
line, that is not available on the slot, I used a WRITE ENABLE LATCH. This
latch is set by READING a memory location. The consequence of seting this
latch is that the output latches will read the data bus during the next
instruction, which will be a memory WRITE that outputs the desired data.
1 - The signals available on the Cartridge Slot
D0..D15 - DATA BUS
A1..A15 - The 15 least significant addresses from the ADDRESS BUS
ROM 3 SELECT - Active when a READ instruction accesses $FB0000 to
$FBFFFF
UDS',LDS' - Upper and Lower Data Strobe
2 - The I/O PORT
The block diagram of the I/O PORT is in the file BLOCKDIA.PI3. Cir-
cuit diagrams are in ADDRESS.PI3 and IN'OUT.PI3. If you don't have these
drawings then in appendix A you can read a description of the circuit.
The circuit of the I/O PORT is standart. A address decoder enables the
output latches or the input buffers when the correct address is accessed.
However, the output latches are only enabled if previously the WRITE ENABLE
LATCH was set.
Address Decoder:
The lines A3..A15 are connected to NAND gates that detect when all
these lines are at high level. The lines A2 and A1, select one of the
four outputs of a decoder.
The output of the NOR gate "a" is active when we read from $FBFFFE.
To decode a read to this address we use the outputs of the two NAND gates,
the output three of the decoder (active when A1 and A2 are high) and the
line ROM 3 SELECT.
The output of NOR gate "a" sets the WRITE ENABLE LATCH.
The output of NOR gate "b" decodes the address $XXFFFC. To decode an
access to these addresses (read or write), we use the outputs of the NAND
gates, output two of the decoder and the line LDS'.
ROM 3 SELECT cannot be used here because it is only active on read.
When a write instruction accesses the address $10FFFC (non-existent
in 1MByte ST's) then the output of NOR gate "b" becomes active.
An AND gate enables the output latches to read the data bus if the
WRITE ENABLE LATCH is set AND the output of NOR gate "b" is active.
The output of NOR gate "b" is delayed (by four inverters) and then
resets the WRITE ENABLE LATCH, just after the latches have read the data
bus.
NOR gate "c" decodes a read to address $FBFFFA, as gate "a" does, but
using output one of the decoder. The output of gate "c" enables the buffers
to copy their inputs to the data bus.
3 - Components
2- 4068 NAND gates for address decoding
2- 4002 NOR gates for address decoding
1- 4556 1 OF 4 DECODER for address decoding
1- 4043 SR FLIP-FLOP write enable latch
1- 4049 INVERTER
1- 4081 AND
2- 40373 LATCHES output latches
1- 74LS244 BUFFERS input buffers
4 - Expansion
This I/O PORT is easily expandable to as many I/O lines you want. Only
one WRITE ENABLE LATCH is necessary if the expansion is made in a way that
any write to port instruction resets the latch. Another solution is to have
a reset latch address (as we have a set latch address). In this case the
write to port instructions don't need to reset the latch, and you can output
a block of data to several addresses without needing to set the latch in
between. Only at the end of the block transfer this would be necessary.
You can have another 8 inputs by just connecting another 74LS244 to
D8..D15 of the data bus.
5 - Software
To write to the output lines the contents of D0:
MOVE.W $FBFFFE,D1 ;D1 is destroyed, latch is set
MOVE.W D0,$10FFFC ;D0 is latched
To read the input lines to D0:
MOVE.W $FBFFFA,D0
6 - Connection to the ST
I could not find a experimentor PC Board with an edge connector that
fits to the ST. So I made a convertor from the 40 pin edge connector (with
spacing of 2mm) to a 64 pins euroconnector (DIN 41612). This convertor is
simply a double sided PCB with 20 lines (on each side) of 1mm spaced by 2mm
(center of one line to center of next line). These lines widen to 2.54 mm
to fit the DIN connector. Line one of the ST goes to line 4 of the DIN
connector. The tabs of the DIN connector are on the lower side.
______
|| |
|. .| 1
|. .| 2
|. .| 3
+ |. .| 4 +
Data 15 |. .| 5 Data 14
|. .|
: | | :
: | | :
| |
Ground |. .| 23 Ground
| |
|. .| 31
|. .| 32
|| | DIN connector seen from front (connection) side
------
I intend to connect some of the free lines of this connector to inter-
nal signals of the ST. Would be nice to have a standart connector between
ST users. Whoever has ideas about which signals to connect and to which
pin should let the others know about it.
7 - Conclusion
It is possible to open the ST !!
And this opens a lot of possibilities in hardware design. The 68000's
power can be used outside the ST's box.
But a complex machine like the ST cannot be easily expanded without
having information about it. The information that ATARI delivers only to
software houses. Please ATARI, let everybody know about the ST. Let the
POWER be available to all users.
Douglas P. B. Renaux
Outshoornstraat 55
5622GX Eindhoven - NL
Tel 31-40-436930
(Address valid until May 25,1986)
People dealing with hardware design
are cordially invited to contact me.
APPENDIX A
Circuit Description.
Block Diagram:
write enable latch
___________ ______
| | Read $FBFFFE | | _____
| |----------------------|S Q|------------| & |
A15..A1 | ADDRESS | $XXFFFC _________ | | | |---|
LDS ----| DECODER |-----T---| Delay |----|R | |----| | |
ROM3 SEL| | | --------- ------ | ----- |
| | |_____________________________| |
| | |
| |-----------| |
----------- Read | |
$ FBFFFA | |---------
--------- ------------
| | | |
| INPUT | D15 | OUTPUT |
D7..D0-----|BUFFERS|---INPUTS --| LATCHES |--OUT
| | D0 | |
| | | |
--------- ------------
Address Decoder Description:
Address lines A15 to A3 are connected to the inputs of two 4068
(8-input NAND). Inputs are pins 2,3,4,5,9,10,11,12. One of these NAND
gates has three inputs tied high. Power supply is connected to pin 14 (+)
and pin 7 (ground).
The address lines A2 and A1 are connected to the select lines of the
4556 (1 of 4 decoder), pins 3 (A2) and 2 (A1). The enable line (pin 1) is
tied low. Pins 16(+) and 8 (ground). The outputs of the decoder are:
output 0 at pin 4, output 1 (pin 5), output 2 (pin 6), output 3 (pin 7).
The second level of the address decoding is done by three NOR gates
of four inputs (4002). Two chips are necessary. These gates are labelled
"a", "b" and "c".
Pinning of the 4002: inputs 2,3,4,5; output pin 1
inputs 9,10,11,12; output pin 13
power: pin 14 (+); pin 7 (ground).
Two inputs of gate "a" are connected to the outputs of the 4068 (pin
13). The third input is connected to ROM3 SELECT and the fourth input goes
to output 3 of the decoder. The output of gate "a" is connected to the SET
input of the WRITE ENABLE LATCH.
Gate "b". Inputs: the two outputs of the 4068s, output 2 of the
decoder and LDS. The output of this gate is the line $XXFFFC of the block
diagram, it goes to a chain of four inverters (4049) to produce a delay,
and it goes to an AND gate.
Gate "c". Inputs: the two outputs of the 4068s, output 1 of the
decoder and ROM3 SELECT. The output of gate "c" is inverted by a 4049
and then connected to the enable line of the input buffers (74LS244).
Delay chain: The hex inverter 4049 (inputs pins 3,5,7,9,11,14; outputs
pins 2,4,6,10,12,15 respectively) is used. Four inverters are chained to
give the desired delay and one inverter is used for the enable of the input
buffer. Power is on pin 1 (+) and pin 8 (ground). Note that + is NOT on
pin 16!
Write enable latch: A 4043 (SR-latch) is used. SET is on pin 4, RESET
on 3 and Q on 2. Pin 5 (output enable) is tied low. Power is on pins 16 (+)
and 8 (ground). SET is connected to the output of gate "a". RESET goes to
the output of the delay chain.
AND gate (4081). Inputs: Q from the latch (connected to pin 1) and
the output of gate "b" (connected to pin 2). The output of this gate (pin 3)
enables the output latches. Power is on pins 14 (+) and 7 (ground).
Output latches. Two 40373 (octal latches) are used. Inputs (pins 3,4,
7,8,13,14,17,18) are connected to the DATA BUS. Outputs (pins 2,5,6,9,12,
15,16,19 respectively) are the outputs of the circuit. Pin 1 (output enable)
is tied low. Pin 11 (enable latches) goes to the output of the AND gate.
Power to pins 20 (+) and 10 (ground).
Input buffers. The 74LS244 (inputs 2,4,6,8,11,13,15,17 outputs 18,16,
14,12,9,7,5,3 respectively). The inputs of these buffers are the inputs of
the circuit. The outputs are connected to the DATA BUS (D0..D7). Pins 1 and
19 (output enable) are connected to the inverted output of gate "c". Power
to pins 20 (+) and 10 (ground).
I used the +5V from the cartridge slot to drive the circuit and 16 leds
that monitor the outputs. (The leds are not connected directly to the 40373,
but via buffers 4049).