[mod.ai] Seminar - Reasoning about Semiconductor Fabrication

pasley@SRI-KL (Christine Pasley) (05/28/86)

		CS529 - AI In Design & Manufacturing
		Instructor: Dr. J. M. Tenenbaum

Title:		Modeling and Reasoning about Semiconductor Fabrication
Speakers:	John Mohammed and Michael Klein
From:		Schlumberger Palo Alto Research and Shiva Multisystems
Date:		Wednesday, May 28, 1986
Time:		4:00 - 5:30
Place:		Terman 556

Abstract for John Mohammed's talk:

As part of a larger effort aimed at providing symbolic, computer-aided
tools for semiconductor fabrication experts, we have developed
qualitative models of the operations performed during semiconductor
manufacture.  By qualitativiely simulating a sequence of these models
we generate a description of how a wafer is affected by the operations.
This description encodes the entire history of processing for the
wafer and causally relates the attributes that describe the structures
on the wafer to the processing operations responsible for creating
those structures.  These causal relationships can be used to support
many reasoning tasks in the semiconductor fabrication domain,
including synthesis of new recipes, and diagnosis of failures in
operating fabrication lines.

Abstract for Michael Klein's talk:

Current integrated circuit (IC) process computer-aided design (CAD)
tools are most useful in verifying or tuning IC processes in the
vicinity of an acceptable solution.  However, these highly
compute-intensive tools are often used too early and too often in the
design cycle.

Cameo, an expert CAD system, assists IC process designers in
synthesizing photolithography step descriptions before using other CAD
tools.  Cameo has a modular knowledge base containing knowledge for all
levels of the synthesis process, including heuristic knowledge as well
as algorithms, formulas, graphs, and tables.  It supports the parallel
development of numerous design alternatives in an efficient manner and
links to existing CAD tools such as IC process simulators.

Visitors welcome!


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