[mod.ai] Seminar - LISP on a Reduced-Instruction-Set Processor

pas@MOJAVE.STANFORD.EDU (Peter Steenkiste) (11/24/86)

		  Special Seminar: Ph.D. Orals

           LISP on a Reduced-Instruction-Set Processor:
                Characterization and Optimization

                         Peter Steenkiste

                   Computer Systems Laboratory
              Department of Electrical Engineering
                       Stanford University


                            Abstract

As a result of advances in compiler technology, almost all programs
are written in high-level languages, and the effectiveness of a 
computer architecture is determined by its suitability as a compiler
target.  This central role of compilers in the use of computers has 
led computer architects to study the implementation of high-level 
language programs.  This thesis presents profiling measurements for
a set of Portable Standard Lisp programs that were executed on the
MIPS-X reduced-instruction-set processor, examining what instructions
LISP uses at the assembly level, and how much time is spent on the
most common primitive LISP operations.  This information makes it
possible to determine which operations are time critical and to
evaluate how well architectural features address these operations.

The second part of the thesis will discuss a number of optimizations 
for LISP, concentrating on three areas: the implementation of the 
tags used for runtime type checking, reducing the cost of procedure 
calls, and inter-procedural register allocation.  We look at methods
to implement tags, both with and without hardware support, and we 
compare the performance of the different implementation strategies.  
We show how the procedure call cost can be reduced by inlining small 
procedures, and how inlining affects the miss rate in the MIPS-X 
on-chip instruction cache.  A simple register allocator uses inter-
procedural information to reduce the cost of saving and restoring 
registers across procedure calls.  We evaluate this register allocation
allocation scheme, and compare its performance with hardware register 
windows.

Time: Monday, December 8, 1986, 4:15pm
Place: CIS Building, Room 101

Cookies will be served!