CLT@SAIL.STANFORD.EDU.UUCP (02/28/87)
Title: VLSI approach to the ELIS Lisp machine Speaker: Yasushi Hibino Director of Second Research Section NTT Basic Research Laboratories Nippon Telegraph and Telephone Time: Monday March 2, 3:30pm Place: 352 Margaret Jacks Abstract: The LISP Machine ELIS was designed to achieve a comfortable interactive programming environment by a fast microcoded LISP interpreter. ELIS is a microprogram control machine with a 32k 64-bits-words writable control store. ELIS also has a 32K word hardware stack and special memory interface registers. VLSI ELIS chip is developed by two-micron double metal layer CMOS technology. The VLSI ELIS is compatible with an ELIS breadboard machine in the level of microcodes. Therefore, TAO Lisp, which is a dialect of CommonLisp and assimilates object oriented programming, logic programming and concurrent programming within the Lisp world, is running on the VLIS ELIS. The speed of interpreted codes in TAO is comparable to that of compiled codes of MIT's Lisp machines. THis good performance is attained by a simple internal bus structure and a design of fucntion blocks with iterative circuit structures. In my talk, the architecture of ELIS is briefly introduced and a VLSI approach for it is discussed. The approach is not like Meed and Conway's. It is rather orthodox approach, because in the case of a dedicated machine it is not desirable that VLSI design methodology restricts an architecture of the machine. [CLT -- Sorry for the short notice, please pass this on to anyone you think might be interested.]