rs@mimsy.umd.edu@mirror.TMC.COM (12/10/86)
According to the \fIComputer Design\fP of 15-Nov-86, the new Pyramid machines have been announced. The Series 9000 (I liked 100x better, but they didn't ask me... :-) is available domestically to OEM's (the first time Pyramid has done that). The 9810 is a single-CPU model; the 9820 is a dual-cpu model. Both will be available first-quarter 87. The 9000 has the same 100-ns cycle time of the 98, and is object- code compatible. It's (at least) twice as fast because they extended the pipeline, so that when it's full the CPU can do one instruction per clock tick. There is 64K of data cache, and 16K of instruction cache. I seem to recall that the caches are split equally between kernal and user space. In addition, there's a new board which handles all address translations. This frees up the old board (E board?) to do things like branch detection and optimize the instruction fetching. The machines are targeted to compete with the VAX 8700 and 8800. The Pyramid 9810 costs $200K, versus $450K for the 8700. (Those prices are from \fICD\fP; don't blame me.)