louie@umd5.UUCP (Louis Mamakos) (06/11/86)
The next few postings describe in detail an expansion board that you can
build to add 1MB of memory and a clock to your amiga. Note that this
memory and clock DOES NOT conform to the standard Amiga expansion
architecture, and as such, won't autoconfig. You probably won't be able
to use a standard expansion box with this either. With that said, here
it is. It was forwarded to me by a friend who got it sent to him by
someone who got if off of a BBS... You get the idea.
I have no idea if this works or not. Hey, it could smoke your system
for all I know. The schematic looks resonable enough, but I'm not a
hardcore hardware hacker.
Do what you wish with it; if it doesn't work, I sure won't be held
responsable. Look at the README file for more info about where it
came from.
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
Start with mem.doc for an overview of the project. This document will
explain the other files.
If you have any comments or questions about the documentation, leave me
Email on the Denver Amiga BBS, (303) 693-4735. If you cannot get the board
to work, please try to get local help from some technical type. I cannot
debug miswiring over the phone.
Several people have asked about expanding the board. I have two
suggestions. If you can, the easy thing to do would be to use 1 meg chips.
These are very expensive at present, but would give you a 4 meg board. The
extra address multiplexer is already there, only a little rework of the
select lines is needed. A second copy of the memory array is possible,
including the drivers. If you do this, you must add another chip to develop
more ras lines. Also, you will have to add a power supply since the Amiga
cannot handle more chips than are on the present design.
This project is released to the public domain for non commercial use. This
entire archive file is copyright 1986 by Michael W. Fellinger, 1590 Quince
Ave. Boulder, Co 80302. Any contributions cheerfully accepted at that
address. Anyone interested in commercial use should contact me first.
My next hardware project for the Amiga will be a cheap hard disk interface.
Anyone interested should leave me Email. At this time, the hardware has been
figured out, but I need a device driver. Help would be appreciated.
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
static int adr[6]={9,8,7,4,2,0};
static char *month[12]={
"Jan",
"Feb",
"Mar",
"Apr",
"May",
"Jun",
"Jul",
"Aug",
"Sep",
"Oct",
"Nov",
"Dec"};
static unsigned char d,i,*adradr=(char *)0x600003,*dataadr=(char *)0x600001;
readclock(data)
char data[];
{
*adradr=0xc;/* check for end of update cycle */
d=*dataadr;
do {
*adradr=0xc;
} while((*dataadr&0x10)==0);
/* here if just completed update cycle */
do {
for(i=0;i<6;i++) {
*adradr=adr[i];
data[i]=*dataadr;
}
*adradr=0xa;
if((*dataadr&0x80)!=0) continue;/* update */
*adradr=0xc;
} while((*dataadr&0x10)!=0);
/* here if read without encountering another update */
}
writeclock(data)
char data[];
{
*adradr=0xc;/* check for end of update cycle */
d=*dataadr;
do {
*adradr=0xc;
} while((*dataadr&0x10)==0);
/* here if just completed update cycle */
do {
for(i=0;i<6;i++) {
*adradr=adr[i];
*dataadr=data[i];
}
*adradr=0xa;
if((*dataadr&0x80)!=0) continue;/* update */
*adradr=0xc;
} while((*dataadr&0x10)!=0);
/* here if written without encountering another update */
}
main(argc,argv)
int argc;
char *argv[];
{
int i;
char data[6];
char string[40];
int day,year,hour,min,sec;
/* check validity of clock */
*adradr=0xa;
if((i=(*dataadr&0x7f))!=0x20)
{
printf("reg a is %d\n",i);
*adradr=0xa;
*dataadr=0x20;
*adradr=0xd;
*dataadr=0;
}
*adradr=0xb;
if((i=*dataadr)!=0x7)
{
printf("reg b is %d\n",i);
*adradr=0xb;
*dataadr=0x7;
*adradr=0xd;
*dataadr=0;
}
*adradr=0xd;
if(((i=*dataadr) != 0x80) && (argc < 3))
{
printf("reg d is %d\n",i);
printf("CLOCK CHIP INVALID\n");
printf("To validate clock chip execute:\n");
printf(" clock dd-mmm-yy hh:mm:ss\n");
exit(30);
}
*adradr=0xd;
*dataadr=0x80; /* set clock ok bit */
readclock(data);
while((argc--)>1){
if(strlen(argv[argc])==9&&argv[argc][2]=='-'&&argv[argc][6]=='-')
{ /* handle date */
sscanf(argv[argc],"%2d-%3s-%2d",&day,string,&year);
if(day>0&&day<32) data[2]=day;
else {
printf("bad day of month\n");
exit(30);
}
for(i=0;i<12;i++) {
for(d=0;d<3;d++) {
if(tolower(string[d])!=tolower(month[i][d])) break;
else if(d==2) data[1]=i+1;
}
if(d==3) break;
}
if(i==12){
printf("bad month\n");
exit(30);
}
data[0]=year;
}
else if(strlen(argv[argc])>4&&argv[argc][2]==':') /* time */
{ /* handle time */
if(strlen(argv[argc])==8&&argv[argc][5]==':')
sscanf(argv[argc],"%2d:%2d:%2d",&hour,&min,&sec);
else {
sscanf(argv[argc],"%2d:%2d",&hour,&min);
sec=0;
}
if(hour>=0&&hour<24) data[3]=hour;
else {
printf("bad hour\n");
exit(30);
}
if(min>=0 && min<60) data[4]=min;
else {
printf("bad minute\n");
exit(30);
}
if(sec>=0 && sec<60) data[5]=sec;
else {
printf("bad second\n");
exit(30);
}
}
else /* syntax error */
{
printf("Incorrect arguements\n");
exit(30);
}
writeclock(data);
}
sprintf(string,"date %2d-%3s-%2d %2d:%2d:%2d\n",data[2],month[data[1]-1],
data[0],data[3],data[4],data[5]);
for(i=0;string[i];i++) {
if(string[i]==' ' && i!=4 && i!=14) string[i]='0';
}
if((!Execute(string,0,0))||(!Execute("date\n",0,0)))
printf("\nDATE INVALID\n");
}
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
4-20pf Var
+-----)|---------+
| |
GND || |
+---||||------+---+----+ 5ea 1N4148
| || 32768Hz | |
| /20M | 5V---|<|-----|<|---+
+---)|---GND \ | 2 +---------+ 24 |
| 10pf / +---+ +----+--|<|----+----|<|---+
| | 3 | | V | G | |
+-------/\/\/-----+--------+ MC14 | B +---)|--N | /
390k 17 | 6818 | B | 1uf D | \ 560
DS---------+ | | +--+ /
14 | [C8] | +--|<|--+ | |
AS---------+ | | | | [10]
18 +-----+ 2 11 | | +-/\/\/-+ | 12v
D7---------+ +---------------+ | 100k | |
17 |74LS | 3 10 | | 18 | |
D6---------+ 245 +---------------+ +------+-----+ |
16 | | 4 9 | | 22 | G |
D5---------+ +---------------+ +------+--)|---N |
15 |[B8] | 5 8 | | 1uf D |
D4---------+ +---------------+ | |
14 | | 6 7 | | 20 |
D3---------+ +---------------+ +----- GND | +
13 | | 7 6 | | ---------
D2---------+ +---------------+ | ------- 4 CELL
12 | | 8 5 | | --------- NICAD
D1---------+ +---------------+ | -------
11 | | 9 4 | | --------- 5 VOLTS
D0---------+ +---------------+ | -------
| | | | |
19 | | 1 15 | | 13 |
SEL*------O| +-------+-------+ |O-----------+ GND
+-----+ | +---------+ |
BRW ---------------------+ |
+-------)-------+
74LS04 [A6] O | |
3 |\ 4 SEL 1 12 +-----+ 9 | |
SEL*----| >O-------+ GND-----+ +----+ |
|/ 2 +--- | | |
LDS----------------+ \ 6 11 |\ 10 AS 11| | 8 |
4 | |O------| >O--------|> |O---+ |
A1-----------------+ / |/ +-----+ | |
1 |\ 2 5 +--- O | |
BRW-----| >O-------+ | | |
|/ VBB | |
74LS20 [A7] | |
2/2 74HC | [A8] |
13 74 | |
5V---------+ O 4 |
12 +--- 2 +-----+ 5 |
SEL----------------+ \ 8 9 |\ 8 GND-----+ +----+
10 | |O--+---| >O----DS | | NOTE:
LDS----------------+ / | |/ 3 | | 6 chips at
5 |\ 6 9 +--- +-----------------------|> |O- A8 and C8
A1------| >O-------+ +-----+ powered
|/ O 1 from VBB
| not from
+---[53] 5v sup
RES*
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
The clock is set by using "clock" just like you would use "date" to set the
regular Amiga clock. When you first build the board, the clock may gain or
loose a few seconds a day. You can correct this by adjusting the variable
capacitor in the clock circuit. The best way to do this requires patience.
Note the amount of error in a known amount of time, say a day or a week.
Make an adjustment of perhaps a quarter turn on the capacitor (remember the
direction). Wait this amount of time again. Note the change in the error.
Now you can correct the capacitor by the proportional amount. If the error
is worse, the capacitor must be turned in the opposite direction from the
first attempt. If the error is of the opposite sense, then the first
adjustment overshot. If a quarter turn is worth a second a day, then to
correct a second a week will require a one twentyeighth turn. Since such
delicate adjustments are hard to make, you may need several tries. You can
quit when the clock is sufficiently accurate for your needs. Ultimately,
the clock can be adjusted for about one second a month error. This may be
more trouble than you wish to take, since correcting the time is a one line
command.
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
The memory system was wirewrapped on a 4.5in by 8.5in board perforated on
.1in centers. This is a standard size available from several vendors. A
connector to fit the Amiga expansion connector is mounted to the board such
that the board will stand beside the Amiga extending from the rear up near
the mouse/joystick connectors. The board is slightly higher than the Amiga
but hasn't gotten in the way for me. The memory array (four rows of eight
chips) is at the top of the board. A fifth row contains the buffers for the
array. Next is the connector for the Amiga. Three rows below the connector
are used for timing logic and the clock. The chips all face the Amiga so
that the wire wrap pins of the chips and the connector face out for easy
testing. (I hope this isn't an issue for you, but I did a lot of it.)
The connector is spaced away from the board by placing a 1/2 inch wide
strip of plastic (made from the tubes that wire wrap sockets come in)
between the rows of pins. This leaves just enough room on the pin on the
back side of the board for one wire to be wrapped on the pin. This allows
the connector to reach into the Amiga and leave room for the chips between
the board and the side of the computer.
TOP
+-------+-------+-------+-------+-------+-------+-------+-------+
| H1 | H2 | H3 | H4 | H5 | H6 | H7 | H8 |
+-------+-------+-------+-------+-------+-------+-------+-------+
| G1 | G2 | G3 | G4 | G5 | G6 | G7 | G8 |
+-------+-------+-------+-------+-------+-------+-------+-------+
| F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 |
+-------+-------+-------+-------+-------+-------+-------+-------+
F | E1 | E2 | E3 | E4 | E5 | E6 | E7 | E8 |
R +-------+-------+-------+--+----+---+---+-------+-------+-------+ B
O | D1 | D3 | D4 | D5 | D7 | A
N +---+-----------+----------+--------+-----------+---------------+ C
T | C O N N E C T O R | | K
+---+---+-------+-------+-------+-------+-------+ C8 |
| C1 | C2 | C3 | C4 | C5 | C6 | |
+-------+-------+-------+-------+-------+-------+---------------+
| B1 | B2 | B3 | B4 | B5 | B6 | B8 |
+-------+-------+-------+-------+-------+-------+-------+-------+
| A1 | A2 | A3 | A4 | A5 | A6 | A7 | A8 |
+-------+-------+-------+-------+-------+-------+-------+-------+
BOTTOM
View of board from wire wrap pin side. You are looking at the right
side of the Amiga if the board is installed. The chip locations are called
out in the schematic and parts list.
The connector is numbered like this:
1.5.........................85 From same view as above.
2...........................86
The schematic calls out pins on this connector like [nn]. If you look in the
hardware manual (preliminary) you may think the connector looks like:
123.........................43
............................86
This is WRONG.
If you cannot find an 86 pin connector with .1in spacing (sometimes called a
43 pin dual row connector) you can cut down a longer connector. I easily
found 100 pin connectors. If you do this be careful when installing the board
that the connector is aligned with the cardedge in the Amiga. It is very
easy to have it slip to the side with one end missing. This will harm the
computer.
When looking at the chips from the back side (as viewed above) the pins are
like this:
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
For 16 pin chips. For other sizes of chip, the numbering goes clockwise as
shown.
All chip sockets, except the 24 pin socket for the MC146818, have a .1uf
capacitor connected between the corner pins 8 and 16 (or 7 and 14 or 10 and
20). There are two techniques that I find convenient. If the type of socket
and the type of capacitor permit, the nicest thing to do is to attach the
capacitor to the socket pins before the socket is pushed into the board. The
socket may permit the capacitor to fit into the cavity usually found between
the rows of pins. The wires will raise the socket only slightly off the
board. If this won't work because of the parts at hand, I usually solder the
capacitors on last, after all wirewrap connections are made. Any other
approach tends to make wirewrapping difficult because the capacitor is in
the way.
I would wrap the power and ground connections first. Make a grid of these
wires such that each ground pin is connected to its nearest neighbors in all
four directions. If your sockets won't accept four levels of wrap, connect
at least three ways so that as much of the grid structure as possible is
maintained. The memory array has many pins that are common to all 32 chips.
These connections are also best made with a grid like pattern. The idea is
to connect all the relevant pins with a minimum of inductance. Since, with
wire wrap, there is no other parameter under your control, redundant
connections are the way to achieve this.
The other connections can be made in any order you like. Minimizing total
wire lengths when connecting several pins is nice, but not strictly
necessary. I made some effort in this direction when I placed the parts and
wired them, but the layout is not optimal in this sense. I don't think it is
necessary to be too concerned with the wirewrapping "rules" for this board.
One thing to attempt to do is to keep wires on the same "level". If you have
four pins (for instance) you connect the first and second, then the third
and fourth, and finally the second and third. Doing things this way means
that when you make a mistake you only have to remove at most three wires to
correct it. You cannot unwrap a wire and re-use it, (if you do, the
connection will probably fail in a few months) so any misconnected wire
must be completely removed. This means any wire covering it must be removed.
Don't daisychain yourself into a situation where many wires must be removed
to correct an error.
There is a variable capacitor in the clock circuit. This is used to adjust
the clock so that it keeps proper time. The capacitor should be mounted so
that it can be adjusted with the board installed and running. Since there
are many styles of capacitor, I cannot suggest any particular method.
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
This document describes the operation and construction of a one megabyte
memory board with optional battery backed up clock for the Amiga. You can
also build a 512k memory by only populating one bank. I do not mention
elsewhere that the software needs to be modified to match the new limits if
you do this.
The memory system consists of two banks of 256k words each. The banks are
selected by the row address strobe (RAS) which is qualified by an address
bit (A19) to select the bank. The upper and lower data strobes are used to
generate seperate column address strobes (CAS) for the upper and lower
bytes. Refresh is accomplished by activating the row address strobes for
both banks while supplying a refresh address. Refresh cycles occur, if
possible, when the memory is not being accessed (because some other resource
is being addressed) or when necessary by holding off the processor to force
time for the refresh cycle. All timing is derived from the 68000 clocks.
This allows a fully synchronous design so that there are no glitches in
timing possible. This also means that the processor must wait one clock
cycle when it accesses this memory. The processor clock is simply too slow
to go through the necessary states without the wait. If one eliminated the
wait the system would be 20% faster. This would require a delay line or an
asynchronous design. The cost of these alternatives is more than I was
willing to pay. Also, the design would be harder to duplicate because of the
more delicate timing.
The clock is a Motorola MC146818. It keeps track of the date and time
including daylight savings and leapyear. A nicad battery is charged by the
Amiga when it is powered up. This battery runs the clock when the Amiga is
off. As long as the Amiga is on 1% of the time, the clock will remain
accurate.
This memory board does not autoconfigure. This means that the Amiga doesn't
know about it until it is told. A program called AddMem is distributed on
the assembler or C disks. This program is needed to tell the Amiga that the
memory exists. I have not written a clone of this program. I have written a
memory test program to test the board. It is included in this release.
At this time, a number of programs, including Deluxe Paint, do not work
properly with external memory. I hope that as more Amigas get added memory
the suppliers of these programs will fix the problems. Mostly, graphics
objects cannot reside in external memory. If a graphics object is a program
constant, the program must be chip memory resident. There is no way to do
this within a language. When a program allocates memory, it must specially
ask for chip memory if needed because the operating system will allocate
>from external memory if it can. If you want to use one of the programs that
does not work with external memory, simply do not use the AddMem command.
There is no need to remove the card. Amiga has released the ATOM program to
developers which is used to tell the loader that some hunks must be loaded
into chip memory. If you can get this program, it will fix the above
problems.
The hardware clock isn't used by the Amiga during normal operation since it
keeps its own internal clock. I have written a program to read the hardware
clock and set the system clock (this is more trouble than I wanted). This
program is also included in this release.
The easiest way to use these new resources is to modify your
s/startup-sequence file to include:
AddMem 400000 500000
Clock
as added commands at the beginning. I also usually copy the entire system
disk to ram: and reassign all the logicals to the copy in ram:. The system
is very fast when running entirely out of ram.
I wirewrapped the memory since I expected to make changes. It took three
tries before the control circuit worked well. There were a number of pins
that were essentially undocumented and I had little choice but to try things
until they worked. Because this design has no support from Amiga, I cannot
guarantee that it works with your machine. On the other hand, I design
memories (and other things) for a living. I know what I'm doing. The design
is very forgiving of small timing changes (another reason to keep it slow)
and I do not expect anyone to have problems. I have no intention of
supplying a PC board. I don't mind if someone else takes on that project as
long as it is non-commercial. (If you are interested in a commercial design
let me know, I would do many things differently if it were a high quantity
commercial product. This design is bent in the direction of ease of
duplication with no special parts.)
There are four additional files I will mention here. The mechanical
description is in mem.mechanical. This includes the connector and board info
and the chip socket locations. Some comments on construction are also
included. The parts list is in mem.parts. The parts given will work.
Substitutions are possible, but at your own risk. The schematic is in
mem.schematic and clock.schematic (this section can be built at a later
time.) This is not the most beautiful method of drawing schematics,
but it allows this project to be electronically documented so it can reach a
lot of people without the 10th generation xerox problem. The schematic files
look best if printed at eight lines per inch.
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
GND [ 1][ 2][ 3][ 4][13][25][37][49][61][73][85]
5V [ 5][ 6]
A20 1 +-------+ 15 E 1 +-------+ 3
[56]-------+ |O---- [50]-----+> +----
A21 2 | | 14 2 | 1/2 | 4
[58]-------+ |O---- RFR -----+ 74LS +----
A22 3 | | 13 | 393 | 5
[57]-------+ |O---- 1/6 | +---- RFD
| | 12 74LS04 | [E2] | 6
| 74LS |O---- | +--+
| 138 | 11 1 |\ 2 +-------+ |
| |O---- ADR* ----| >O---- ADR +---------+
6 | [A1] | 10 |/ +---+ +--------- 5V
5V ----+ |O---- | O 4
A23 5 | | 9 [B3] |2 +-------+ 5
[59]------O| |O---- SEL* +--+ 1/2 +---- RFRQ
4 | | 7 | 74LS |
GND ----O| |O---- | 74 |
+-------+ AS* 3 | | 6
[74]--+----+> [B4] |O----
5 | +-------+
ADR------+ | O 1
4 +--- | 2/6 +-------- RFRAS*
AS-------+ \ 6 | 74LS04
2 | |O---+ | 5 |\ 6
RFC*-----+ / | 1/3 74LS10 +----| >O---- AS
1 +--- | |/
PRCH*----+ | 3,4 +---
74LS20 +-----+ \ 6 13 |\ 12
[A2] 5 | |O---- MRAS --------| >O---- MRAS*
13 +-----+ / |/
RFRQ-----+ | +---
12 +--- | [B3]
ADR*-----+ \ 8 | [A4]
10 | |O---+ +---- 5V
AS-------+ / O 4
9 +--- 2 +-------+ 5
RFC*-----+ MRAS---+ 1/2 +---- MUX
| 74LS |
| 74 |
11 3 | | 6
RFD------+--- CDAC*---+> [A3] |O---
10 | \ 8 4 +-------+ 2 +-------+
MRAS*----+ |O-------+ +----- RFC* O 1
9 | / | | 3 AS-----+
HOLD*----+--- | |O----
5 | | 7 +----5V
RFC* ----+ 74SL +----- RFRAS* O 10
| 175 | 6 12 +-------+ 10
| |O---- RFRAS MUX----+ 1/2 +---- CAST
12 | [A5] | 10 | 74LS |
RFRAS* -----+ +----- PRCH* | 74 |
| | 11 CDAC 11| | 9
| |O---- [15]+--+> [B4] |O---
13 | | 15 | +-------+
CAST -------+ +----- HOLD | O 13
9 | | 14 | +----AS
CDAC* ------+> |O---- HOLD* |
+-------+ | 3 |\ 4
O 1 +----| >O----CDAC*
1/4 74LS00 +----5V |/
1 +--- [B3]
ADR ----+ \ 3
2 |[B5] |O---- RCYC
RFC* ---+ /
+---
2/4 74125 [D4]
2 |\ 3 5 |\ 6
HOLD* ----| >----[66] DTACK* ADR*---+----| >------[18] XRDY
|/O | |/O
1| | | 4
| +------+
+--- ADR*
2/6 74LS04 [B3]
11|\ 10 9 |\ 8
UDS* [72]------| >O------ UDS LDS* [70]-------| >O------- LDS
|/ |/
3 11
CAST ------+--- 2/3 74LS10 CAST ------+---
4 | \ 6 10 | \
UDS -------+[B1] |O----- UCAS* LDS -------+[B1] |O----- LCAS*
5 | / 9 | /
MCYC ------+--- MCYC ------+---
13
12,13 |\ 11 10 +--- 5V----+---
A19 [54]---+---| >O--------+ \ 8 2 | \ 12
| |/ 9 | |O----------+[A4] |O----- RAS1*
| RFR ---+ / 1 | /
| +--- RAST ---+---
|
| 3/4 74LS00 [B5]
| 13
| 4 +--- 5V----+---
+---------------+ \ 6 2 | \ 12
5 | |O----------+[B1] |O----- RAS0*
RFR----+ / 1 | /
+--- RAST ---+---
12,13|\ 11 10 +---
MCYC*-------| >O-------- MCYC MRAS* ----+ \ 8
|/ 9 | |0---- RAST
4/4 74LS00 [B6] RFRAS* ---+ /
+---
1 +---
RFRQ* -----+ \ 3 4 +---
2 | |O-----+-------+ \ 6
RFRAS* ----+ / | 5 | |O------ RFR*
+--- +-------+ /
+---
13 +-------+ 11
RFR--------O|> +-------- RA0
| 1/2 | 10
| 74LS +-------- RA1
| 393 | 9
| +-------- RA2
12 | [B2] | 8
+------+ +---+---- RA3
| +-------+ |
GND |
+----------------+
|
| 1 +-------+ 3
+---O|> +-------- RA4
| 1/2 | 4
| 74LS +-------- RA5
| 393 | 5
| +-------- RA6
2 | [C6] | 6
+------+ +---+---- RA7
| +-------+ |
GND |
+----------------+
|
|13 +-------+ 11
+---O|> +-------- RA8
| 1/2 | 10
| 74LS +--------
| 393 | 9
| +--------
12 | [C6] | 8
+------+ +--------
| +-------+
GND
A10 6 +-------+ 7
[34]--------+ +------------- MA0
A1 5 | 74LS | 15
[29]--------+ 153 |O----+
4 | or | 1 |
RA0 ---+----+ 74LS |O----+
| 3 | 253 | |
+----+ | GND
A11 10 | [C1] | 9
[36]--------+ +------------- MA1
A2 11 | |
[27]--------+ |
12 | | 2
RA1 ---+----+ +-------- RCYC
| 13 | | 14
+----+ +-------- MUX*
+-------+
A12 6 +-------+ 7
[38]--------+ +------------- MA2
A3 5 | 74LS | 15
[26]--------+ 153 |O----+
4 | or | 1 |
RA2 ----+---+ 74LS |O----+
| 3 | 253 | |
+---+ | GND
A13 10 | [C2] | 9
[39]--------+ +------------- MA3
A4 11 | |
[24]--------+ |
12 | | 2
RA3 ---+----+ +-------- RCYC
| 13 | | 14
+----+ +-------- MUX*
+-------+
A14 6 +-------+ 7
[41]--------+ +------------- MA4
A5 5 | 74LS | 15
[21]--------+ 153 |O----+
4 | or | 1 |
RA4 ---+----+ 74LS |O----+
| 3 | 253 | |
+----+ | GND
A15 10 | [C3] | 9
[43]--------+ +------------- MA5
A6 11 | |
[23]--------+ |
12 | | 2
RA5 ---+----+ +-------- RCYC
| 13 | | 14
+----+ +-------- MUX*
+-------+
A16 6 +-------+ 7
[45]--------+ +------------- MA6
A7 5 | 74LS | 15
[28]--------+ 153 |O----+
4 | or | 1 |
RA6 ---+----+ 74LS |O----+
| 3 | 253 | |
+----+ | GND
A17 10 | [C4] | 9
[47]--------+ +------------- MA7
A8 11 | |
[30]--------+ |
12 | | 2
RA7 ---+----+ +-------- RCYC
| 13 | | 14
+----+ +-------- MUX*
+-------+
A18 6 +-------+ 7
[52]--------+ +------------- MA8
A9 5 | 74LS | 15
[32]--------+ 153 |O----+
4 | or | 1 |
RA8 ---+----+ 74LS |O----+
| 3 | 253 | |
+----+ | GND
10 | [C5] | 9
+--------+ +------------- MA9
| 11 | |
+--------+ |
| 12 | | 2
+--------+ +-------- RCYC
| 13 | | 14
+--------+ +-------- MUX*
| +-------+
GND
2 +-------+ 18
MA0 --------+ +-------- p5 all memory chips
17 | 74HC | 3
MA1 --------+ 244 +-------- p7
4 | or | 16
MA2 --------+ Am +-------- p6
15 | 2966 | 5
MA3 --------+ +-------- p12
6 | | 14
MA4 --------+ +-------- p11
13 | | 7
MA5 --------+ +-------- p10
8 | [D3] | 12
MA6 --------+ +-------- p13
11 | | 9
MA7 --------+ +-------- p9
| | 1
| |O---+
| | 19 |
| |O---+
+-------+ |
GND
2 +-------+ 18
MA8 ---------+ +-------- p1 of all memory chips
17 | 74HC | 3
UCAS --------+ 244 +-------- p15 of rows 1-4
4 | or | 16
LCAS --------+ Am +-------- p15 of rows 5-8
15 | 2966 | 5
RAS0 --------+ +-------- p4 of rows 1,3,5,7
6 | | 14
RAS1 --------+ +-------- p4 of rows 2,4,6,8
R/W 13 | | 7
[68]---------+ +-------- BRW and p3 of all memory chips
8 | [D5] | 12
+----+ +---
| 11 | | 9
+----+ +---
| | | 1
GND | |O----+
| | 19 |
| |O----+
+-------+ |
GND
D15 18 +-------+ 2
[63]---------+ +-------- p2,p14 of E1,E2
D14 17 | 74LS | 3
[65]---------+ 245 +-------- p2,p14 of F1,F2
D13 16 | | 4
[67]---------+ +-------- p2,p14 of G1,G2
D12 15 | | 5
[69]---------+ +-------- p2,p14 of H1,H2
D11 14 | | 6
[71]---------+ +-------- p2,p14 of E3,E4
D10 13 | | 7
[76]---------+ +-------- p2,p14 of F3,F4
D9 12 | | 8
[78]---------+ +-------- p2,p14 of G3,G4
D8 11 | | 9
[80]---------+ +-------- p2,p14 of H3,H4
| [D1] |
19 | | 1
ADR* -------O| +-------- BRW
+-------+
D7 18 +-------+ 2
[82]---------+ +-------- p2,p14 of E5,E6
D6 17 | | 3
[84]---------+ 74LS +-------- p2,p14 of F5,F6
D5 16 | 245 | 4
[86]---------+ +-------- p2,p14 of G5,G6
D4 15 | | 5
[83]---------+ +-------- p2,p14 of H5,H6
D3 14 | | 6
[81]---------+ +-------- p2,p14 of E7,E8
D2 13 | | 7
[79]---------+ +-------- p2,p14 of F7,F8
D1 12 | [D7] | 8
[77]---------+ +-------- p2,p14 of G7,G8
D0 11 | | 9
[75]---------+ +-------- p2,p14 of H7,H8
| |
19 | | 1
ADR* -------O| +-------- BRW
+-------+
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
main(argc,argv)
long argc;
char *argv[];
{
unsigned short *adr;
int i,j,k,n;
adr=0x0400000;
for(i=0;i<0x010000;i++)
{
for(j=0x000000;j<0x080000;j++)
{
adr[j]=j+i+j>>12;
}
for(j=0x000000;j<0x080000;j++)
{
k=adr[j];
n=(j+i+j>>12)&0x0ffff;
if((n!=k)&&(argc>1))
printf("wrote %4x read %4x diff %4x at addr %6x\n",n,k,n^k,&adr[j]);
}
}
}
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louielouie@umd5.UUCP (Louis Mamakos) (06/11/86)
Parts list for one megabyte memory board with clock
Chips
2 74LS00 B5, B6
2 74LS04 A6, B3
2 74LS10 A4, B1
2 74LS20 A2, A7
2 74LS74 A3, B4
1 74HC74 A8
1 74125 D4
1 74LS138 A1
5 74LS153 C1, C2, C3, C4, C5 (May be 74LS253)
1 74LS175 A5
2 74LS393 B2, C6
2 74HC244 D3, D5 (May be Am2966, NOT 74LS244)
3 74LS245 B8, D1, D7
1 MC146818 C8
32 Rams E1 thru H8 (May be any 256k by 1 dynamic ram at 200ns
or faster access time. I have tried
several brands, both CMOS and NMOS, with
no problems.)
Capacitors
48 0.1 uf ceramic cap 12v or higher (bypass caps at each chip, not on schem.
2 1.0 uf ceramic or tantalum, 12v or higher
1 10 pf NP0 ceramic or mica
1 4-20 pf variable (substitute any cap that covers 7-15 pf range)
Diodes
5 1N4148, 1N914 or equivalent
Resistors all 1/4 watt 5% film
1 560 ohm
1 100k
1 390k
1 22M if not available substitute 10M
Crystal
32768 Hz watch crystal
Battery
4 Nicad cells with holder. Either A or C size is ok.
Sockets
14 14 pin wire wrap sockets. I substituted 16 pin for a price break.
39 16 pin wire wrap sockets.
5 20 pin wire wrap sockets.
1 24 pin .6 in spacing wire wrap socket.
--
Louis A. Mamakos WA3YMH University of Maryland, Computer Science Center
Internet: louie@trantor.umd.edu
UUCP: {seismo!umcp-cs, ihnp4!rlgvax}!cvl!umd5!louiekellym@shark.UUCP (Kelly McArthur) (06/13/86)
In article <1021@umd5.UUCP> louie@trantor.umd.edu (Louis Mamakos) writes: > > > > 2/4 74125 [D4] > 2 |\ 3 5 |\ 6 > HOLD* ----| >----[66] DTACK* ADR*---+----| >------[18] XRDY > |/O | |/O > 1| | | 4 > | +------+ > +--- ADR* To quote from document "Designing Hardware for the Amiga Expansion Architecture": 2.2.1 Read or Write Cycle with Amiga as Master Since the Amiga bus master is a 68000, the bus cycle is a 68000 cycle. However, the responding slave does not pull DTACK*. Our internal circuitry will pull DTACK* unless the slave pulls XRDY low. Elsewhere, in the document "INTERFACING TO THE 68K CONNECTOR ON THE AMIGA", it states: 2.2 Bus Timing ...Two control inputs, VPA* and DTACK* are driven by logic on the Amiga and should not be driven by your circuitry. Since in the above schematic, DTACK* is shown as being driven by a '125 under some condition it appears likely that this could result in a tri-state contention over DTACK*. This is not good. A few changes to the XRDY* logic would eliminate the need for that driver all together. Kelly McArthur ...tektronix!shark!kellym