hull@hao.UUCP (Howard Hull) (08/15/86)
Yes, there is something different about powering up compared to powering down. In the days of memory chips that had multiple power supply voltage pins, designers (DEC on LSI11's, for instance) began to discipline their power supply systems by including IC op-amp integrators to control the ramp-up rates of various power supplies. Specifications for various chips required that some voltages "stay ahead" of others on ramp-up. In multiple power supply systems this was very beneficial, even for chips that didn't have multiple power pins, as it kept input signals and output load returns proportionally between the rail voltages and prevented blasting the on-chip clamp diodes. The best that could be done on power-down was to place over-clamp diodes between the most positive supply and any lesser-voltage supplies (anode connected to the lesser voltage supply). Similarly, diodes could be used for negative-going supply sets (anode connected to most negative supply). As a consequence, on power-down, even though voltages are kept between the major rails, proportionalities between supplies are not preserved, and logic is sometimes perverse; particularly when the switch bounces or power rebounds and then croaks (as during a pre-failure brown-out). Howard Hull [If yet unproven concepts are outlawed in the range of discussion... ...Then only the deranged will discuss yet unproven concepts] {ucbvax!hplabs | decvax!noao | mcvax!seismo | ihnp4!seismo} !hao!hull