jeff@gatech.EDU (Jeff Lee) (09/29/86)
> Using the untranslated addresses as the RAS addresses and doing the MMU > address translation before the column addresses are needed for CAS sounds > pretty general to me. I am sure the process Andy Bechtolsheim patented is > quite a bit more specific. A patent cannot be granted for a general idea. > It requires a specific implementation of an idea, either in a device or > process. Think about it. Without that provision patents would stifle > development. They are intended to do just the opposite. A patent is > supposed to protect the inventor of a process from those who would use his > work as their own. But it is not supposed to prevent people from using a > concept the inventor has brought to light in their own inventions, so long > as they don't plaigiarize from the original work. I have a copy of the patent in front of me and I'm afraid that it is quite general. They explain things in term of a general MMU that accepts the address bus, uses direct address lines and indirect address lines, a timing generator, and main memory. They then give a specific example that they are running that uses segmentation and paging on the upper address lines. They speak specifically about using dynamic rams (actually any rams that use row and column address strobes), and using the untranslated address lines before the translated address lines to increase the breathing room for translation. I'll quote the important section where he is actually telling what the invention is. --------------------------- begin quote mode ----------------------------- Disclosure of Invention An object of the invention is to minimize the delay incurred by a memory management unit in accessing a computer memory. The above object of the invention is realized by overlapping the delay time through the memory management unit with the access of memory. This is achieved by a computer memory addresses with row and column addresses and a memory management unit that allows low order addresses to pass directly into the row address of the computer memory whereas the high-order addresses pass through the memory management unit and enter the column address of the computer memory. The system utilizes an address bus extending from a processor to a memory management means. The address bus splits memory addresses into pre-defined direct and indirect address segments. The direct address segments are fed directly to a computer main memory array of the type having rows and columns of control lines for bit storage elements which are located at intersections of the control lines. While the direct address segments are fed to either of the rows or columns of the main memory, the indirect address segments are fed to a memory management means which translates the indirect segments to a physical address. The translated indirect address segments are then fed to the other of the rows or columns of the main memory array, so that rows and columns of the main memory array are controlled by the direct address segments on the one hand and the translated indirect address segments on the other hand. The rows and columns of the mins array have connected driver circuits for enabling access to the storage elements. A timing generator is provided for strobing the row and column driver circuits with sequential pulses. While the direct address segmentsarrive first at main memory, and are strobed first, the translated indirect address segments arrive shortly thereafter and are strobed second, thereby permitting access to storage locations in main memory. The time between the two strobing pulses is used for indirect address translation, reducing memory access time. In addition, the invention minimizes the address translation time of the memory management unit by using a high-speed static RAM (random- access-memory) for the translation process and by using the same RAM address lines both for address input and for accessing the entries of the memory management means in order to modify the translation. ----------------------------- end quote mode ----------------------------- This also looks, now that I have read it while typing it in, like they are also patenting using a high speed ram as the memory management storage device. This is even more general than people probably realized, but when I was looking into patents, the suggestion was to make it as general as possible so you could better protect the heart of the process. Anyway, if anyone would like a copy of the entire patent (6 pages) you can send $2 to me and I'll mail you back a copy. This won't quite cover the expense of getting it to you, but it will deter people who aren't really interested in it that much and keep me from going broke sending out a hundred of these. I'll pay for the envelope and the return postage. Just send your mailing address to: Jeff Lee c/o School of ICS Georgia Tech 225 North Avenue Atlanta, GA. 30332 I would suggest that you check your local library or maybe a college library someplace close. This will save you $2 and a couple of weeks time. -- Jeff Lee CSNet: Jeff @ GATech ARPA: Jeff%GATech.CSNet @ CSNet-Relay.ARPA uucp: ...!{akgua,allegra,hplabs,ihnp4,linus,seismo,ulysses}!gatech!jeff