wapd@houxj.UUCP (Bill Dietrich) (05/08/85)
I have answered the following questions via private mail
for one person, and maybe posting this will help
other people. Also, I give some pointers to other
information. "It" refers to AT&T's WE 32100 chip-set
(WE 32100 CPU chip, WE 32101 MMU, etc). "WE" is
a trademark of AT&T.
If anyone else has questions, feel free to send mail
to me or post an article, and I'll get answers.
Bill Dietrich
ihnp4!houxj!wapd
AT&T Information Systems
Holmdel, NJ
------------------------------------------------------------
Does it have registers?
CPU has 16 32-bit registers. One is PC,
three are privileged (PSW, ISP, PCBP),
three generally used for procedure linkage
(SP, AP, FP), other 9 generally used
as "general purpose". All but PC are
usable in all addressing modes.
How long does a memory cycle take?
3-cycle access from CPU, add 1 or 2 cycles
for MMU (depends on memory speed and control).
A "cycle" is a CPU clock cycle, which
is 100 nsec for a 10 MHz CPU.
What kind of addressing modes are available?
17 modes, I think. No auto-increment
or auto-decrement.
Does it have any on-chip cache?
WE 32100 CPU has on-chip 256-byte instruction
cache, directly mapped as 32 2-word blocks.
(A word is 32 bits in our terminology).
How much time penalty does branching incur?
I'm not sure. I think it takes 7 cycles for branch
not taken and 9.5 cycles for branch taken.
These are gross averages over all types of code,
and I'm not sure if these are branches with
byte or halfword displacements.
Does it have separate I/O addressing a la Intel,
or is I/O memory mapped?
I/O is memory mapped. There are no "I/O"
instructions, registers, etc.
Can instructions operate on 8, 16, and 32-bit data?
Yes, and in signed or unsigned mode on any size.
Do the operands have to be aligned in memory?
Yes, data words have to be word-aligned
and data halfwords (16 bits) have to be
halfword-aligned. Instructions can start
on any byte boundary.
Can it do a 32-bit multiply and divide?
Yes, hardware supports 32-bit multiply, divide
and modulo.
Does it have string handling instructions?
Yes, string-copy and find-end-of-string.
Strings are defined as 0-byte-terminated
byte-strings as in C.
Does it have bit field instructions?
Yes, EXTFW and INSFW extract and insert
bit-fields from and into 32-bit words.
The bit fields can not cross word boundaries.
There is also a large complement of
AND, OR, XOR, arithmetic shift and logical
shift instructions on all data types.
Where to call for more information ?
If you want data sheets call (800) 372-2447.
------------------------------------------------------------
Published References :
C. T. Cheney, E. B. Kozemchak, "The AT&T WE 32100 Microsystem Product
Line" - CompCon '85 (Feb.).
M. H. Clark, R. A. Rango, K. J. Rusnock, W. A. Stubblebine,
"Hardware/Software Development System for the WE 32100 CPU and MMU"
- WESCON 1984.
M. L. Fuccio, L. N. Goyal, "Hardware Configuration and I/O Protocol
of the WE 32100 Microprocessor Chip Set" - WESCON '85.
A. D. Berenbaum, M. Condry, P. M. Lu, "The Operating System and Language
Support Features of the BELLMAC-32 Microprocessor",
Symposium on Architectural Support for Programming Languages
and Operating Systems, March 1-3 1982, Palo Alto, California,
pages 30-38.
P. M. Lu, W. A. Dietrich, Jr., M. L. Fuccio, "Architecture
of a VLSI Map for BELLMAC-32 Microprocessor", Spring COMPCON 83,
February 28 - March 3 1983, San Francisco, California, pages 213-217.
A. K. Goksel, Phil W. Diodato, John A. Fields, Ulhas V. Gumaste,
Chew K. Kung, Kingyao Lin, Mario E. Lega, Peter M. Maurer,
Thomas K. Ng, Yaw T. Oh, Mark E. Thierbach, "An IEEE Standard
Floating Point Chip", ISSCC 1985, February 1985, pages 18+19.
------------------------------------------------------------