janzen@pldvax.DEC (Tom J. LMO2-1/E5 279-5421) (03/24/86)
>One of the most common ways of building a digital delay line is to construct >a box something like this: > > <____feedback path___<_ > \ \ >input -> a/d converter -> bucket-brigade memory -> d/a converter -> output > | > control > >The idea is simple; the input signal is digitized (converted from an analog >waveform to a series of binary words of some size, typically 8-14 bits) and >fed into a large chunk of memory. Each lil' chunk of memory passes the word(s) >along to the next; eventually, after some time has passed, it pops out the >end other end. It is there converted back to an analog waveform, (optionally) >filtered, and there's your delayed signal. This "explanation" uses anachronistic terminology incorrectly. A "bucket-brigade" is an analogue circuit which passes stored voltages (or charges if you like) from little op-amp circuit to op amp, or from fet to fet in a Charge-Coupled device. Digital delays do not use "bucket-brigades." Digital delays are digital becuase they use digital computer memories to store the sound. Digital delays require Analogue-to-Digital convertors (ADCs)and Digital-to-Analogue Converters(DACs) to format the sound for the memory. The computer memory, a Random-Access-Memory (RAM), stores the music in samples taken by the ADC and its conditioning circuits. The reading circuits reads from the RAM and sends one data word at a time to the DAC and its conditioning circuits to the line level output. It is possible to build analogue delays with op-amp and switched circuits, or with monolithic Charge-coupled device delays, which move each charge of electricity (each of which represents a sample, in which the charge changes size with the voltage of the input) along a snake-like path to the output. CCDs are limited to about 1024 samples on a chip, and are prone to noise of various types, so chaining chips to accumulate delay. is not desirable. Digital (computer) memory-based delays are not limited in size, only by money. A 5-minute delay would probably cost about $2000 in parts, for example. A cheap 2 second delay is now $240. I know it's not proportional. I am designing a harmonizer. CCDs can be used to make a harmonizer (instantaneous universal transposer); digital memories can also. Tom Janzen DEC 111 Locke Marlboro MA 01752
rsk@pucc-j (Wombat) (03/27/86)
In article <1848@decwrl.DEC.COM> janzen@pldvax.DEC (Tom J. LMO2-1/E5 279-5421) writes: >A "bucket-brigade" is an analogue circuit which passes stored voltages... >I also meant to say that this M.O. is dead wrong. Modern delays use >RAMs, and the data does not snake its way through the memory, although it >does through CCDs, which are not digital. >CCDs are limited to about 1024 samples on a chip, and are prone to noise >of various types, so chaining chips to accumulate delay. is not desirable. Oh, get stuffed! I used simplistic terminology *correctly*, in attempting to explain the fundamentals of digital delays. I am perfectly aware of the use of RAM-based implementations in some modern units; however, I felt that it wasn't necessary to explain the complex model when the simple one would do. However, it would appear that you are unaware of the existence of digital CCD's, which are frequently used in applications where random access is not required -- and that's a lot of applications. CCD memories [Such as the TI 3064] are frequently referred to as "bucket-brigade" devices, since the digital signal propagates through them in much the same way that an analog signal propagates through an analog delay line. There's no need for fancy addressing schemes and fast RAM if all you want to do is delay a signal for a fixed period of time or similar simple tasks. Your nitpicking, followed by a substantially similar explanation, sheds no additonal light on the subject. >I am designing a harmonizer. Fine. Let's compare credentials. The digital delay I designed is in use daily in hundreds of studios and radio stations around the country, was one of the first (if not the first) to use a variable loopback in order to shift time without changing the pitch, and earned a patent for the manufacturer, as it was the first to use a digital delay line based on CCD's, along with companding ADC/DAC circuitry. -- Rich Kulawiec pucc-j!rsk or rsk@asc.purdue.edu
gibson@unc.UUCP (Bill Gibson) (03/28/86)
Expires: References: Sender: >> Of course, a long hardware shift register should be easier to control >> than the RAM, but I didn't realize that such a register exists (unless >> you're referring to an analog bucket-brigade delay line). >Yes... there is a 1024-bit shift register, the SAD-1024, made specifically >for this purpose. Aha! This tells me what we have been talking about. I remember the SAD-1024 being a *S*tereo *A*nalog *D*elay, a bucket-brigade delay in which charge sloshes along in 2 lines of 512 buckets each. I think that the device was originally designed to be used with analog inputs and outputs, but I guess you could shift bits through it instead. If this device is used as a digital shift register, is the noise introduced by the charge-transfer between buckets small enough so that bits reliably pass through? I think the SAD-1024s I got were about $11 each. If you consider the device to be a 1024 bit shift register, this means that they have a cost/bit of about $.01/bit. The following pricing is taken from net.micro.atari (referring to a 520ST upgrade): > 16 256K * 1 RAM chips, 150 ns access time type, e. g. NEC 41256C-15 > (available at Fry's Electronics, Sunnyvale, CA for $2.77 ea.) This is about $.01/Kbit, or about a thousand times cheaper than the SAD-1024. Although the SAD-1024 might be easier to control, the difference in price could buy a lot of control hardware for the RAM! If I were interested in long delay times and high-frequency sampling, I'd probably design with the RAM instead of the SAD-1024. Bill Gibson gibson@unc ...[akgua,decvax,philabs]!mcnc!unc!gibson
jer@peora.UUCP (J. Eric Roskos) (03/31/86)
> Aha! This tells me what we have been talking about. I remember the > SAD-1024 being a *S*tereo *A*nalog *D*elay, a bucket-brigade delay in > which charge sloshes along in 2 lines of 512 buckets each. I think that > the device was originally designed to be used with analog inputs and > outputs, but I guess you could shift bits through it instead. If this > device is used as a digital shift register, is the noise introduced by the > charge-transfer between buckets small enough so that bits reliably pass > through? Actually, the 2 applications I used an SAD-1024 in [which were both designed by other people] used it as a digital device; I hadn't realized it could be used as an analog device until it was mentioned in here! Although actually it was a sort of "digital circuits used by analog engineers" hybrid approach (see below). > This is about $.01/Kbit, or about a thousand times cheaper than the > SAD-1024. Although the SAD-1024 might be easier to control, the > difference in price could buy a lot of control hardware for the RAM! I agree with that, though. However, the problem really is that I was thinking in analog synthesizer mode [the above synthesizers used a "top octave generator" and then used plain TTL gates to divide down and narrow the pulses before putting them into a small mixing and filter circuit that included the SAD-1024; i.e., much like your typical electronic organ circuit -- it had something like 900 diodes alone, and took about 40 hours to assemble... however, it gave better sound than any pure digital synthesizer I've seen, eventhough it could only make 3 distinct voices] whereas you were thinking in digital mode, which is more reasonable nowadays. I have a hard time getting used to these machines that can do 8 times more than the old-fashioned ones on a 4x5 circuit board... :-) (The above synthesizer -- I forget the model number, it was PAIA's old string synthesizer -- required two boards that were each about 4 inches by 2.5 feet, not including the one that had the SAD-1024 on it). -- E. Roskos