josh@polaris.UUCP (Josh Knight) (07/10/85)
%A Robert C. Stanley
%T Microprocessors in Brief
%J IBM J R&D
%V 29
%N 2
%P 110-131
%D MAR 1985
%X This paper presents a tutorial overview of the past, present, and future
of microprocessors and describes the key elements of their structure and
operation. It is intended to serve as a technical introduction to the
rapidly expanding field of microprocessor and microcomputer technology and
to provide an overview of what these elements are, what they can do, and
how they do it. The origin and evolution as well as the basic principles
of operation are discussed. Several different types of microprocessor
are considered and examples of their application in the solution of
real-world problems are given.
%A G. Ungerboeck
%A D. Maiwald
%A H.-P. Kaeser
%A P.R. Chevillat
%A J.P. Beraud
%T Architecture of a Digital Signal Processor
%J IBM J R&D
%V 29
%N 1
%P 132-139
%D MAR 1985
%X A digital signal processor (DSP) is described which achieves high
processing efficiency by executing concurrently four functions in every
processor cycle: instruction prefetching from a dedicated instruction
memory and generation of an effective operand, access to a single-port
data memory and transfer of a data word over a common data bus,
arithmetic/logic-unit (ALU) operation, and multiplication. Instructions
have a single format and contain an operand, index control bits, and
two independent operation codes called "transfer" code and "compute"
code. The first code specifies the transfer of a data word over the
common data bus, e.g. from data memory to a local register. The
second determines an operation of the ALU on the contents of local
registers. A fast free-running multiplier operates in parallel
with the ALU and delivers a product in every cycle with a pipeline
delay of two cycles. The architecture allows transversal-filter
operations to be performed with one multiplication and ALU operation
in every cycle. This is accomplished by a novel interleaving technique
called ZIP-ing. The efficiency of the processor is demonstrated by
programming examples
%A Jean Paul Beraud
%T Signal Processor Chip Implementation
%J IBM J R&D
%V 29
%N 1
%P 140-146
%D MAR 1985
%X Very large microprocessors can now be integrated on a single chip; the
integration eliminates packaging delays and is especially attractive for
performance-oriented processors such as signal processors. This paper
describes a semicustom signal processor chip designed jointly by IBM France
Essonnes and La Gaude laboratories. The logic is implemented from an
optimized library of bipolar circuits. Layouts are compatible and designed
to map data flow structures efficiently. Chip design time has been greatly
reduced through the use of developed CAD tools tailored to our methodology.
The design achieves twice the density that would be possible (with the same
technology) with a masterslice. The chip's high performance has been verified
with hardware; it provides enough computation power for 125 second-order
filters with 8-kHz sampling of the input signal.
%A C. Galand
%A C. Couturier
%A G. Platel
%A R. Vermot-Gauchy
%T Voice-Excited Predictive Coder (VEPC) Implementation on a High-performance
Signal Processor
%J IBM J R&D
%V 29
%N 1
%P 147-157
%D MAR 1985
%X In this paper, we discuss the implementation of a medium-bit-rate linear
prediction baseband coder on an IBM bipolar signal processor prototype having
a high processing capacity. We show that the implementation of our algorithm
requires a processing load of 5 MIPS, with a program size of 5K instructions.
We than discuss the application of our coder in a normal telephone environment,
which requires mu-law to linear PCM conversion and other signal processing
functions such as voice activity detection, automatic gain control, echo
control, and error recovery. Quality evaluation tests are also reported which
show that this type of coder, operating at 7.2 kbps, allows the transmission
of telephone speech with communications quality. Moreover, obtained
intelligibility scores and speaker recognition levels are high enough to
demonstrate that this coder is a good candidate for telephony.
%A G. Shichman
%T Personal Instrument (PI) - A PC-based Signal Processing System
%J IBM J R&D
%V 29
%N 1
%P 158-169
%D MAR 1985
%X The Personal Computer (PC) technology has seen an enormous growth in
the last two years. Although increasingly viewed as a major productivity
tool, the PC is likely to be limited for computation-intensive tasks such
as telecommunications and improved human-factors I/O. At the same time,
there has been another evolving technology - VLSI realization of general-
purpose signal processor (SP) engines which are capable of boosting the
performance levels of standard PCs by almost two orders of magnitude.
With SPs in PCs, we now see tremendous opportunities for distributing
computation-intensive tasks away from high-performance mainframe computers;
previously formidable tasks such as speech coding and recognition, pattern
and scene analysis, spectral analysis, high bit-rate communication, and
the like are now all computable by utilizing a single VLSI module embedded
in any standard personal computer. This combination of a general-purpose
CPU and a superfast real-time coprocessor is likely to be key to the
future functions and success of advanced workstations. A signal processing
subsystem with real-time data acquisition and control capabilities has been
developed for the IBM P-C at the IBM Thomas J. Watson Research Laboratory
and is the topic of this paper.
%A James T. Rayfield
%A Harvey F. Silverman
%T An Approach to DFT Calculations Using Standard Microprocessors
%J IBM J R&D
%V 29
%N 1
%P 170-176
%D MAR 1985
%X The use of the DFT as an everyday tool is now commonplace, principally
due to advances in hardware technology. Special-purpose VLSI chips for
signal processing are available. In this paper, we describe an approach
which marries the Winograd Fourier Transform Algorithm (WFTA) with a state-
of-the-art 16-bit general-purpose microprocessor for the purpose of DFT
calculation. The heart of the approach is the real-input 240-point WFTA,
which has been carefully optimized for time and space. In particular,
an implementation for the 10-MHz M68000 executes in 10.8 ms. A simple
hardware module is described which implements the optimized software.
The sue of the module for the inverse transform and for the complex case
is also discussed. Advantages to the approach taken in this paper are the
low cost/performance ratio and the general-purpose nature of the system
that allows many non-signal-processing functions to be performed by
the microprocessor.
%A M. Abrams
%A A. Blusson
%A V. Carrere
%A T. Nguyen
%A Y. Rabu
%T Image Processing Applications for Geologic Mapping
%J IBM J R&D
%V 29
%N 1
%P 177-187
%D MAR 1985
%X The use of satellite data, particularly Landsat images, for geologic
mapping provides the geologist with a powerful tool. The digital format
of these data permits applications of image processing to extract or enhance
information useful for mapping purposes. Examples are presented of lithologic
classifications using texture measures, automatic lineament detection and
structural analysis, and use of registered multisource satellite data. In
each case, the additional mapping information provided relative to the
particular treatment is evaluated. The goal is to provide the geologist
with a range of processing techniques adapted to specific mapping problems.
%A Stephen Todd
%A Glen G. Langdon, Jr.
%A Jorma Rissanen
%T Parameter Reduction and Context Selection for Compression of Gray-Scale
Images
%J IBM J R&D
%V 29
%N 1
%P 188-193
%D MAR 1985
%X In the compression of multilevel (color or gray) image data, effective
compression is obtained economically be judicial selection of the predictor
and the conditioning states or contexts which determine what probability
distribution to use for the prediction error. We provide a cost-effective
approach to the following two problems: (1) to reduce the number of coding
parameters to describe a distribution when several contexts are involved,
and (2) to choose contexts for which variations in prediction error
distributions are expected. We solve Problem 1 (distribution description)
by a partition of the range of values of the outcomes into equivalence
classes, called buckets. The result is a special decomposition of the
error range. Cost-effectiveness is achieved by using the many contexts
only to predict the bucket (equivalence class) probabilities. The
probabilities are assumed to be independent of the context, thus enormously
reducing the number of coding parameters involved. We solve problem 2
(economical contexts) by using the buckets of the surrounding pixels as
components of the conditioning class. The bucket values have the desirable
properties needed for the error distributions.
%A Peter J. Haas
%A Gerald S. Shedler
%T Regenerative Simulation Methods for Local Area Computer Networks
%J IBM J R&D
%V 29
%N 1
%P 194-205
%D MAR 1985
%X Local area computer network simulations are inherently non-Markovian in
that the underlying stochastic process cannot be modeled as a Markov chain
with countable state space. We restrict attention to local network simulations
whose underlying stochastic process can be represented as a generalized
semi-Markov process (GSMP). Using "new better than used" distributional
assumptions and sample path properties of the GSMP, we provide a "geometric
trials" criterion for recurrence in this setting. We also provide conditions
which ensure that a GSMP is a regenerative process and that the expected time
between regeneration points is finite. Steady-state estimation procedures
for ring and bus network simulations follow from these results.
------
Josh Knight, IBM T.J. Watson Research
josh at YKTVMH on BITNET, josh.yktvmh.ibm-sj on CSnet,
...!philabs!polaris!josh