jayar@utcsrgv.UUCP (Jonathan Rose) (02/17/84)
_M_i_n_u_t_e_s _F_r_o_m _t_h_e _O_c_t_o_b_e_r _2_0 _V_L_S_I _F_o_r_u_m
_C_h_a_i_r_m_a_n: Martin Snelgrove
_S_e_c_r_e_t_a_r_y: Jonathan Rose
1. _M_a_r_t_i_n__S_n_e_l_g_r_o_v_e__-__T_h_e__F_a_i_r_c_h_i_l_d__E_L_E_C_T_R_I_C__C_A_D__P_a_c_k_a_g_e
Prof. Snelgrove has sent away for a CAD package from Fair-
child, called ELECTRIC. It costs only $200 and looks worth
investigating. It has the following features:
- it has a hierarchical layout editor that allows top
down design.
- it will maintain conectivity upon movement such as
stretching (rubber banding).
- supports NMOS,CMOS,BJT,Bulk CMOS, Printed Circuit
Boards plus a mixture of the above. (seemingly fantas-
tic, but this remains to be seen)
- incremental design rule checking - when you change an
item in the layout it will let you know if this cause a
design rule violation.
- can be linked to ESIM (a relative of MOSIM) and also
MARS, which is a hierarchical switching simulator.
- uses the CORE graphics package, and supports the AED512
and the Ikonas.
- claims that a 10,00 transistor design was done in a
week, using ELECTRIC.
- some of the recomended potential extensions to the sys-
tem are: mechanical CAD, 3D CAD and 4D (animation)
- work was done by the Artificial Intelligence people at
Fairchild in C/Unix.
- Prof. Vinod Agarwaal at McGill (who has been trying to
get it running on Eunice on a VAX all summer) said that
the code is "spaghetti-like". It just goes to show
that some programmers can write FORTRAN in any
language.
- the license is for non-commercial use only, but the
source is available to all of U of T. It comes with a
manual and a library of cells.
- it is not supported.
- 2 -
2. _B_r_i_a_n__T_h_o_m_s_o_n__-__C_M_U__D_A__s_y_s_t_e_m
Hubnet is currently purchasing three CAD programs from Carnegie-
Mellon university. One of the programs is a circuit extracter -
that described in the 83 Design Automation Conference, and is
called "ACE". It is reportedly quite fast. The other programs
are a Wirelist comparator called Gemini and a Design Rule
Checker. Gemini is reportedly quite fast and produces CIF output
that, when displayed, will hilite netlist diferences. Hubnet is
also obtaining WOMBAT from Berkely, another netlist comparator.
Peter Boulton is actively engaged in soliciting tools from Berke-
ley. Apparently it is now easier to obtain tools from Berkeley
than it was a year ago. This is evidenced by the fact that
Waterloo has the entire Berkeley VLSI CAD distribution tape.
3. _T_e_t__Y_e_a_p__&__W_a_i_-_H_u_n_g__L_o
Tet and Wai are working on a VLSI implementation of the VASTOR 1
bit array processor. An NMOS and CMOS prototype has been sent to
Northern Telecom (via the Queens VLSIIC).
4. _N_e_w_s__o_f__N_e_x_t__V_L_S_I_I_C__R_u_n
Jaro Pristupa reminds all that the deadline for the next VLSIIC
fabrication is January 4/84. All designs should be submitted to
him.
5. _D_i_s_c_u_s_s_i_o_n__o_n__S_i_l_i_c_o_n__F_o_u_n_d_r_i_e_s
- VASTOR may do 1 or more Silicon Foundry runs when it is con-
vinced that reasonable results will occur.
- MICROTEL PACIFIC RESEARCH is a Canadian Silicon Foundry.
Simon Fraser University in the person of R. Hobson is using
the Foundry. We have the design rules for that foundry.
6. _1_6_0_0_0__W_o_r_k_S_t_a_t_i_o_n
Martin Snelgrove gave an update of the status of the 16000
workstaion:
- there will be printed circuit board versions of the system
in January
- the boards will cost $2000.
- the unity operating system largely works
- 3 -
- both the user and system software is still being worked on.
- it needs a network - possibly HUBNET
7. _V_L_S_I__R_e_s_e_a_r_c_h__G_r_o_u_p
Martin Snelgrove gave some information about the newly formed
"VLSI Research Group". It consists of the resident Computer
Group Profs (Vranesic,Loucks,Zaky, and Hammacher), the Electron-
ics Group Profs (Sedra, Salama, Snelgrove, (Holmes?)), and Prof
K.C. Smith, and CSRG Profs Boulton and Lee. Prof Salama is the
chairman and Prof. Snelgrove is the secretary. (But can he
type?) A Brochure is being produced to fully describe the group.
It's mandate is to
- coordinate VLSI efforts
- maintain a list of equipment available for VLSI research
- Tax its members to obtain funds for more equipment
- exchange and obtain software assests.