jayar@utcsrgv.UUCP (Jonathan Rose) (02/17/84)
_M_i_n_u_t_e_s _F_r_o_m _t_h_e _O_c_t_o_b_e_r _2_6 _V_L_S_I _F_o_r_u_m
_C_h_a_i_r_m_a_n: Martin Snelgrove
_S_e_c_r_e_t_a_r_y: Jonathan Rose
1. _S_u_m_m_a_r_y__o_f__T_h_e__C_a_n_a_d_i_a_n__V_L_S_I__C_o_n_f_e_r_e_n_c_e__-__J_o_n_a_t_h_a_n__R_o_s_e
The first annual Canadian Conference on VLSI was held in Waterloo
on October 24/25, 1983. Universities from across Canada partici-
pated and display their various capabilities (or lack thereof) in
VLSI design and manufacturing.
The only paper from U of T was given by Tet Yeap (co-
authors: Wai Hung Lo, Martin Snelgrove, Wayne Loucks and Safwat
Zaky) on the subject of the VASTOR prototype.
A few interesting facts garnered at the conference from
talking to people:
- Waterloo just received a $1.6M strategic grant from NSERC
for its "VLSI Research Group" to work on VLSI CAD and
design.
- Waterloo _d_o_e_s have the Berkeley VLSI CAD tools tape (spring
distribution). So far they only have Caesar working from
that tape. It is running on their Unix Vax and drives an
Orcatech that pretends to be an AED512. (they wrote the
program for the Orcatech emulation)
- Prof. Vinod Agarwaal at McGill (who, as mentioned previ-
ously, has a copy of the ELECTRIC package, but doesn't have
it working) also said that there is a "better" (better than
Caesar) Graphics editor called "KIC" (I'm not sure if
that's spelled correctly) that can be obtained from a group
called DECUS. DECUS is DEC's software distribution group.
- From Doug Colton of Northern Telecom/BNR: Northern is wil-
ling to distribute two thirds of their Standard Cells to the
universities if it is clear that there is a desire for them.
Apparently, some un-named Professors refused them when they
were offered, so Dr. Colton assumed that this was the gen-
eral attitude. He did say that if he received enough
letters to the opposite effect, that he would release them.
Various local professors have undertaken to do so immedi-
ately.
The following is a quick summary of some of the interesting
papers at the conference. (If anyone wishes to see the proceed-
ings, see Jonathan Rose, Tet Yeap, Wai Hung Lo, or Wayne Loucks)
- 2 -
- _P_L_A _G_e_n_e_r_a_t_i_o_n _U_s_i_n_g _a _S_i_l_i_c_o_n _A_s_s_e_m_b_l_e_r given by Glenn
Gulak of the University of Manitoba (formerly of U of T).
They have produced a program that takes input that is a com-
bination of CIF and PLA generation commands, and produces a
layout with the PLA and PADs. Wiring must be done manually.
The PLA generator takes ordinary Boolean equations as input.
Available to all.
- _A_n_a_l_y_s_i_s _o_f _A_D_A _a_s _a _H_i_g_h _L_e_v_e_l _H_a_r_d_w_a_r_e _D_e_s_c_r_i_p_t_i_o_n
_L_a_n_g_u_a_g_e given by Emil Girzyc of Northern Telecom/Carleton
University. It is a preamble to his Ph.D. thesis that is on
Silicon Compilers. Claims that many of the features of ADA
make it amenable to describing hardware. For example, ADA
Tasks allow the description of parallelism in hardware. The
major problem is timing constraint specification - this is
handled by special functions that generate timing references
and subsequent constraints. [A lively discussed ensued on
the suitability of ADA for anything, and what would make a
good hardware description language.]
- _C_A_D _f_o_r _V_L_S_I - _T_h_e _S_t_a_t_e-_o_f-_t_h_e-_A_r_t given by David Agnew of
Northern Telecom. Interesting observation: VLSI-involved
companies now have at least as many CAD people as designers,
and some have three times as many. (Remainder of talk was
motherhood issues such as top down, hierarchical design with
structured approaches, good graphics etc. etc.)
- "Computer Animation as a Tool for VLSI Design" given by
Laurent Langlois of McGill. Basically the idea is to animate
results of a simulator to give a better user interface.
Further papers of interest at the conference will be discussed at
the next VLSI forum.