jayar@utcsrgv.UUCP (Jonathan Rose) (02/17/84)
_M_i_n_u_t_e_s _F_r_o_m _t_h_e _N_o_v_e_m_b_e_r _1_0 _V_L_S_I _F_o_r_u_m
_C_h_a_i_r_m_a_n: Martin Snelgrove
_S_e_c_r_e_t_a_r_y: Jonathan Rose
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Copies of a list (dated June 83) of various CAD tools available
from U.S. universities were handed out. If you want a copy, see
Jonathan Rose (or mail to "jayar"). The list contains a descrip-
tion of some Berkeley tools, some tool from Carnegie-Mellon and a
few other universities.
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The following papers, which represent a subset of the papers at
the Canadian Conference on VLSI, were briefly reviewed.
- An Expandable, Fully Asynchronous CMOS Static RAM For Cell
Library Use, given by W. Snyder of Pacific Microtel
Research. Interesting in that the memory was parameterized
- you could specify the word size and a few other things,
and the cell and drivers pop out.
- Computer Animation as a Tool for VLSI Design, given by
Laurent Langlois of The University of Montreal. The idea is
to use animation to display the results of circuit simula-
tion. You would actually watch a layout change colour,
indicating the voltage changes taking place.
- Testability and VLSI, given by Franc Brglez of Northern
Telecom. A new method for determining the testability of a
circuit was presented. This is part of a larger effort by
Northern to incorporate Design For Testability into its chip
design system.
- Designing a CMOS Cell Library for the SJ16 Microprocessor,
given by Richard Hobson of Simon Fraser University. The
SJ16 is a microprocessor designed to run APL. It was
designed entirely by Hobson on an HP desk top computer using
CAD tools he wrote himself. He gained some IC design
experience while on sabbatical at Microtel Pacific Research.
He has some interesting data on creating a cell library.
- A CMOS VLSI Sieve, given by C.D. Patterson of the University
of Waterloo. This is a VLSI chip that can implement any kind
of sieve. Interesting application of hardware to a specific
problem.
- A Personal Workstation Based Interactive Graphics Editor For
VLSI Layout, given by D. Glendinning of Carleton University.
- 2 -
Carleton has a network of 18 workstations that run VLSI
design software that they have written. Each workstation is
a Corvus 68000 machine with a 760x512 black and white moni-
tor. It may not be much but it works and they use it.
Interlude: What does U of T have and Intend to get in the way of
personal workstations? (i.e. Something for the masses to do IC
design on)
Answer: All we have now are 3 AED 512's hooked to the ECF vax.
(plus sundry other Orcatechs, and Ikonasi that are not generally
available). In the works is the idea that there will be alot of
16000 workstations (made right here at U of T) for people to work
on, each with decent colour graphics, and maybe even a network.
This however is for sometime in the future, after the machine
works, and enough money is found to make them. General murmur-
ings by Stew Lee to the effect that proposals are being sent to
Deans of Faculties, but who knows what will happen?
- PLATO - A PLA/FSM Compiler, given by G. Baker of the Univer-
sity of Waterloo. They have a working program that takes
the description of a Finite State Machine in equation form,
and produces a chip out. It does this by using PLAs and
registers. It has a Pascal-like syntax and outputs CIF, and
runs under UNIX. They will shortly be willing to distribute
it, provided you have something to offer them.
- A Prototype Digital CMOS Cell Library for Systematic Custom
VLSI Applications, given by M.A. Krause of Queens' Univer-
sity. They successfully fabricated some NMOS standard cells
and are now working on CMOS cells, some of which work. They
seem to be they only people who got working NMOS chips back
- mildly suspicious given that the VLSI implementation cen-
tre is at Queens. Doug Colton of Northern Telecom said
something like "Queens chips were the only ones without
design errors." (note a direct quote) If this is so, why
weren't we informed of our design errors?
3. _M_D_C__W_a_n_t_s__S_o_m_e_o_n_e__t_o__w_o_r_k__o_n__t_e_s_t_a_b_i_l_i_t_y__-__A_d_r_i_a_n__H_a_r_t_o_g
The Microelectronic Development Centre might be interested in
having a graduate student work on the problem of testing gate
array circuits, after fabrication. This is a largely algorithmic
problem, so someone working in graph theory in Computer Science
who wanted some real-life practicality would be a good candidate.
If you know of such a person, refer him/her to Adrian Hartog.
(login name utecfa!adrian).
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Adrian has compiled information of alot of the VLSI workstations
available today - see him if you would like to look at it.
5. _L_a_s_t _B_N_R/_N_T _F_a_b_r_i_c_a_t_i_o_n _R_u_n _A_c_c_e_p_t_e_d _b_y _Q_u_e_e_n_s - _J_a_r_o _P_r_i_s_-
_t_u_p_a
The last batch of CMOS chips sent to the VLSI Implementation Cen-
tre has been processed and is on its way to BNR/NT. There is no
news concerning the earlier fabrication run of NMOS.