jayar@utcsrgv.UUCP (Jonathan Rose) (02/17/84)
_M_i_n_u_t_e_s _F_r_o_m _t_h_e _F_e_b_r_u_a_r_y _2/_8_4 _V_L_S_I _F_o_r_u_m _C_h_a_i_r_m_a_n: Martin Snelgrove _S_e_c_r_e_t_a_r_y: Jonathan Rose 1. _L_a_y_o_u_t__o_f__t_h_e__V_A_S_T_O_R__P_r_o_c_e_s_s_o_r__-__T_e_t__Y_e_a_p The latest versions of VASTOR submitted for fabrication (to BNR) were shown, plotted out. The first chip tests the ALU, the I/O pads and a few simple gates. It (and the others) use standard cells with a 40 lambda pitch. The second chip is an entire VASTOR processing element. The third is two VASTOR processing elements configured as VASTOR would actually be used - i.e. there are connections for many more processing elements, should the fabrication rules allow bigger chips. It should be very interesting to see what these chips can do when (?) they come back, as they test very simple things (gates,pads) and more complicated structures (ALUs, processors). Anyone doing any large scale work should pay close attention. 2. _P_a_r_a_m_e_t_e_r_i_z_a_b_l_e__C_e_l_l_s__-__C_a_t_h_y__M_c_q_u_e_e_n Dynamic Parametrizable Cells for Custom VLSI Design: A binary tree data structure was suggested for cell representation, whose capabilities include, cell modification(resizing transistors based upon performance requirements,reconfiguring # of inputs,...) drawing themselves graphically deriving their own connectivity performing logic simulation and connecting with other cells in a general layout. The tree structure contains information on large cells, sub cells, transistors in those cells, wires in the cells and so on. Design Rule Checking can be made easier because location informa- tion is inherent in the data structure. The structure also makes circuit extraction easy because is already contains most of the information required for circuit extraction in the data explicitly. An NMOS and a CMOS parameterizable inverters have been designed and are being used to test expansion algorithms. - 2 - 3. _R_o_a_d__T_r_i_p__T_o__W_a_t_e_r_l_o_o If you are interested in going to the University of Waterloo to see the state of their CAD and design (and perhaps foster cooperation between the two universities) please mail me ("jayar"). Let me know if you have a car, and if you can, in general, go on a Friday.