itrctor@csri.toronto.edu (Ron Riesenbach) (04/17/89)
9 _F_U_T_U_R_E _D_I_R_E_C_T_I_O_N_S _I_N _V_L_S_I _D_E_S_I_G_N
Lectures by two leading experts in VLSI design tools.
Hosted by Professor Glenn Gulak
&
Presented by:
_I_n_f_o_r_m_a_t_i_o_n _T_e_c_h_n_o_l_o_g_y _R_e_s_e_a_r_c_h _C_e_n_t_r_e
Date: Wednesday, May 3, 1989.
Time: 10:00 - 12:30
Location: University of Toronto, Galbraith Bldg. Rm 248, 35 St. George
Street., Toronto.
_A_S_I_C _A_r_c_h_i_t_e_c_t_u_r_e_s _a_n_d _S_y_n_t_h_e_s_i_s _T_o_o_l_s _f_o_r _D_i_g_i_t_a_l _S_i_g_n_a_l _P_r_o_c_e_s_s_i_n_g _D_e_s_i_g_n_s
Dr. Francky Catthoor, Inter-University Microelectronics Consortium (IMEC),
Leuven, Belgium
Many digital signal processing systems operate at low to medium speeds
such as most speech, audio, telephone and telecom applications. For these
application domains, a customized multi-processor architectural methodology
has been defined at IMEC which merges the goals of efficiency in terms of
area and throughput, and the possibility to support it with an "automated"
synthesis toolbox (Cathedral-II project). Cathedral-II starts from a
high-level behavioral description of the DSP algorithm and maps it into an
application-specific architecture, and from that to a layout. In order to
support high throughput video as well as image and radar processing appli-
cations, other target architectures are currently being investigated.
Specifically, multiplexed cooperating bit-sliced data-paths with hard-wired
hierarchical controllers and regular arrays are under study. CAD systems
to support the high-level synthesis of these two hard-wired architectures
are also under way (Cathedral-III and IV environments).
_S_y_s_t_e_m _L_e_v_e_l _C_A_D: _T_h_e _N_e_w _F_r_o_n_t_i_e_r
Dr. David Agnew, Bell Northern Research, Ottawa, Ontario
CAD tools for VLSI have, for some time, been consolidating on a pla-
teau based on gate level logic design. However, the increasing complexity
of VLSI devices and systems is causing a growing need for more abstraction
and simplification of design using CAD. The most promising tools include
synthesis tools, which automatically generate gate level schematic netlist
information for the designer from a higher level description; and design
aids which help the designer create, verify and optimize higher level
descriptions. These aids include tools for mixed textual and graphical cap-
ture of system specs, architecture and behaviour; new simulation and formal
verification tools; multi-paradigm design tools eg. for mixed
hardware/software systems; and newly emerging frameworks and standards for
CAD tools and data, permitting faster and easier development and applica-
tion of new tools.
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This event is free to all industrial affiliates of the ITRC as well as
faculty and students at the participating institutions. Industrial affili-
ates are invited to join the speakers for lunch and a tour of the VLSI
design laboratories after the talks. Industrial affiliates are requested
to register for this event by phoning Rosanna Reid at (416) 978-8558 by
April 28th, 1989.
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