kateveni@su-shasta.arpa (09/06/84)
From: Manolis Katevenis <kateveni@Shasta>
.ft G
.LP
.nr PS 11
.nr VS 16
.LP
.ce 100
EpilogII apO tis protAseis KatebaInii pros tiin omAda Ma:'i:strou
giA ElliinikII metAfrasii 'orwn \fL Hardware \fG
KrIItii, IoUliis 1984.
[mEsa se [ ] siimeiWnetai ii antIstoichii prOtasii tiis omAdas Ma:'i:strou]
(taxinOmiisii alloU katA 'ennoia, kai alloU lexikografikA)
.ce 0
.ft L
.TS
center;
l l.
_
logic circuit \fG logikO kYklwma [logikO kYklwma] \fL
software \fG softgouEar [logikO] \fL
hardware \fG charntgouEar [ylikO] \fL
(transistor) \fG (tranzIstor) \fL
bit \fG mpit [mpit] \fL
flip-flop \fG flip-flop [flip-flop] \fL
_
activate \fG energopoiW [energopoiW] \fL
deactivate \fG adranopoiW [ ] \fL
excite, excitation \fG diegeIrw, diEgersii [ ] \fL
enable \fG epitrEpw [epitrEpw] \fL
disable \fG apotrEpw [apotrEpw] \fL
inhibit \fG apagoreUw [ ] \fL
trigger \fG pyrodotW [energopoiW] \fL
edge-triggered (f-f) \fG akmopyrodOtiito (f-f) [ ] \fL
totem-pole gate \fG pYlii-tOtem [ ] \fL
tri(three)-state (gate) \fG trikatAstatii (pYlii) [ ] \fL
set \fG ?? \fL
reset \fG ?? \fL
preset \fG ?? \fL
_
.TE
.bp
.TS
expand;
l l.
_
NOR gate \fG pYlii-OYTE [pYlii 'ochi-'h] \fL
NAND gate \fG pYlii-OCHI-KAI [pYlii 'ochi-kai] \fL
AND (OR) gate \fG pYlii-KAI (H) [pYlii kai ('h)] \fL
NOT gate \fG pYlii-OCHI [pYlii 'ochi] \fL
AND, OR AND, OR \fG [kai, 'h] \fL
NOT NOT \fG ['ochi] \fL
NAND, NOR NAND, NOR \fG ['ochi-kai, 'ochi-'h]\fL
exclusive-NOR gate (XNOR) \fG pYlii-isOtiitas, pYlii-apokleistikO-oYte
[apokleistikO 'ochi-'h] \fL (XNOR)
exclusive-OR gate (XOR) \fG pYlii-apokleistikO-H \fL (XOR)
And-Or-Invert (AOI) \fG Kai-H-AntistrofII \fL (AOI) [ ]
wired-logic (-AND, -OR) \fG kalwdiwmEnii(o)-logikII (-KAI, -H) [ ]\fL
_
RAM, ROM, PROM, PLA RAM, ROM, PROM, PLA [ ]
Random Access Memory \fG MnIImii TychaIas ProspElasiis [MnIImii
giA TychaIa ProspElasii] \fL
Read-Only Memory \fG MnIImii AnAgnwsiis M'ono [MnIImii
Mono giA AnAgnwsii] \fL
Programmable Logic Array \fG ProgrammatizOmenii ParAtaxii LogikIIs
(PylWn) [ ] \fL
SSI, MSI, LSI, VLSI SSI, MSI, LSI, VLSI \fG [OMIK, OMESK,
OMEK, OPOMEK] \fL
Large Scale Integration,...\fG OloklIIrwsii MegAliis KlImakas,...
[OloklIIrwsii MegAliis KlImakas,...]\fL
_
.TE
.bp
.TS
expand;
l l.
_
ASCII ASCII [ ]
_
Binary-Coded-Decimal (BCD) \fG DekadikO-KwdikopoihmEno-se-DyadikO \fL (BCD) [ ]
block \fG mplok [<domikII monAda>] \fL
block-diagram \fG diAgramma twn (me) mplok [schiimatikO diAgramma] \fL
_
carry \fG kratoUmeno [ ] \fL
carry lookahead \fG prOblepsii kratoumEnou [ ] \fL
chip \fG tsip [psiifIda] \fL
_
debounce circuit \fG ?? [ ] \fL
Dual-In-Line package (DIP) \fG syskeuasIa \fL DIP, DIP,
\fG diplo-grammikII syskeuasIa [ ] \fL
_
encode(r) \fG kwdikopoiW(htIIs) [egkwdikopoiW] \fL
_
hazard \fG ?? [ ] \fL
_
IC IC \fG [OK] \fL
I/O I/O \fG [E/E] \fL
invalid \fG 'akyros [ ] \fL
_
Metal-Oxide-Semiconductor, \fG (syskeuH) MetAlou-OxeidIou-HmiagwgoU,\fL
MOS [Metal-Oxide-Silicon] MOS [ ]
_
probe \fG ?? [ ] \fL
pull-up \fG ?? [ ] \fL
_
race (condition) \fG (synthIIkii) kyniigiitO (oU) [ ] \fL
_
sense amplifier \fG ?? [ ] \fL
seven-segment display \fG endeIktiis-eptA-kommatiWn (??) [ ] \fL
socket (for IC) \fG bAsii (olokliirwmEnou) [ ] \fL
strobe \fG ?? [ ] \fL
switching circuit \fG ( kYklwma diakoptWn (???) ) \fL
_
timing \fG chronismOs [ ] \fL
toggle \fG ?? [ ] \fL
two's (2's) complement \fG symplIIrwma-ws-pros-dYo (2) [ ] \fL
_
up-counter \fG metriitIIs-pros-ta-pAnw [ ] \fL
up/down counter \fG metriitIIs-pAnw/kAtw [ ] \fL
_
.TE