[net.micro.6809] SS-50, SS-50C Bus Description and History

jlw@ariel.UUCP (J.WOOD) (08/07/85)

				  - 1 -



       The following article was copied	without	permission from:


	       `68' Micro Journal
	       5900 Cassandra Smith Rd.
	       Hixson, TN 37343
	       USA

       in its September, 1979 edition.	This is	actually a press
       release from SWTPc, an early supporter of the SS50 bus.

       Once upon a time	in a hobbyist's	world far far away there
       existed two busses fighting for the love	of the people.	The
       S100 bus, developed by Altair for the first popular home
       computer	the Altair 8800, had 100 pins and generally
       followed	the bus	signals	of the 8080 processor.	The later
       arrival,	the SS50 bus, had 50 pins and was developed by
       Smoke Signal Broadcasting for Motorola 6800 processors and
       generally follows the Motorola bus conventions.	For timing
       information see Motorola	specification sheets.  The S100	bus
       sought great heights and	became an IEEE standard, but sank
       into oblivion taking all	with it	with the advent	of the IBM
       PC.  Some even fell before this event Altair, IMSAI, and
       later Altair's parent Pertec.  Most of the original SS50	bus
       people are still	around,	SWTPc, GIMIX, Smoke Signal, and
       Helix.

       Physically the SS50 mother board	had two	sections, the 50-
       Pin section and the 30-Pin section.  The	boards were
       typically a ground plane	on the top with	plated through
       holes to	the bus	lines beneath.	In this	case the pins were
       on the mother board and the sockets were	on the cards.  You
       pays your money and you takes your choice.  The pins
       themselves were Molex pins, mounted five	to a strip of
       Teflon and soldered to the board.  There	were corresponding
       sockets in strips of five which were soldered to	the cards
       to form lines.  The 50-Pin portion of the bus had full
       capability such as DMA, but the other portion of	the bus,
       the 30-pin bus, could only support programmed I/O.  They
       were cheap.  While the S100 crowd was spending $150 for an
       I/O card, we spent $35 for a single port ACIA interface.
       Typically there was logic on the	mother board between the
       50-pin bus and the 30-pin bus to	decode the high	order
       addresses for the 30-pin	bus I/O	Select lines.  My SWTPc
       system had the I/O placed firmly	at 32K,	and at every 8K	for
       the rest	of address space, according to MIKBUG standards.
       After all who'd ever need or be able to afford more than
       32K?

       Here's where the	article	starts.	 In this article ~SOMETHING
       means an	active low signal.  There may be a couple of cases











				  - 2 -



       there you see slash-1 or	slash-2.  This is supposed to be
       Phase 1 or Phase	2 of the two phase clock standard in
       Motherola systems.  The pins are	listed in two columns
       reading from right to left facing the component side of the
       circuit cards.  Typically in an SS50 system if the 50-pin
       boards go front to back,	the 30-pin boards would	go from
       left to right with the components facing	right.	The pins
       for the 30-pin bus are also from	right to left looking at
       the component side of the board.	 Early SS50 systems had
       baud rate clocks	on the processor cards.	 Later on with the
       advent of SS50C the baud	rate clocks were put on	the mother
       boards along with the address decode logic.  This freed up
       the pins	for addressing larger spaces than 64K.



			 SSSSSSSS----55550000 CCCC BBBBuuuussss DDDDeeeessssccccrrrriiiippppttttiiiioooonnnn

       In order	to take	full advantage of the additional features
       in the 6809 processor, the following changes have been made
       in the bus assignments.	All SWTPC peripherals for 6809
       systems will use	the SS-50C specifications listed below.

			  55550000----PPPPIIIINNNN BBBBUUUUSSSS AAAASSSSSSSSIIIIGGGGNNNNMMMMEEEENNNNTTTTSSSS
	    SSSSSSSS----55550000      SSSSSSSS----55550000CCCC	    SSSSSSSS----55550000	    SSSSSSSS----55550000CCCC
	   6666888800000000	BBBBUUUUSSSS   6666888800009999 BBBBUUUUSSSS	  6666888800000000 BBBBUUUUSSSS	   6666888800009999	BBBBUUUUSSSS
	     ~D0	~D0	     GND	     GND
	     ~D1	~D1	     GND	     GND
	     ~D2	~D2	 7-8 VDC UNR	 7-8 VDC UNR
	     ~D3	~D3	 7-8 VDC UNR	 7-8 VDC UNR
	     ~D4	~D4	 7-8 VDC UNR	 7-8 VDC UNR
	     ~D5	~D5	     -12	     -16
	     ~D6	~D6	     +12	     +16
	     ~D7	~D7	    INDEX	    INDEX
	     A15	A15	   ~M.RST	    M.RDY
	     A14	A14	    ~NMI	    ~BUSY
	     A13	A13	    ~IRQ	     ~IRQ
	     A12	A12	     UD2	    ~FIRQ
	     A11	A11	     UD1	      ~Q
	     A10	A10	     ~2		      E
	      A9	 A9	    ~VMA	     ~VMA
	      A8	 A8	    R/~W	     R/~W
	      A7	 A7	   ~RESET	    ~RESET
	      A6	 A6	     BA		      BA
	      A5	 A5	      1		      BS
	      A4	 A4	    ~HALT	    ~HALT
	      A3	 A3	    100b       ~BUS REQ	or 110b
	      A2	 A2	    150b	 S3 or 9600b
	      A1	 A1	    300b	 S2 or 4800b
	      A0	 A0	    1200b	 s1 or 1200b












				  - 3 -



			  33330000----PPPPIIIINNNN BBBBUUUUSSSS AAAASSSSSSSSIIIIGGGGNNNNMMMMEEEENNNNTTTTSSSS

	    SSSSSSSS----33330000      SSSSSSSS----33330000CCCC	    SSSSSSSS----33330000	    SSSSSSSS----33330000CCCC
	   6666888800000000	BBBBUUUUSSSS   6666888800009999 BBBBUUUUSSSS	  6666888800000000 BBBBUUUUSSSS	   6666888800009999	BBBBUUUUSSSS

	     UD3	RS2	     D4		      D4
	     UD4	RS3	     D5		      D5
	     -12	-16	     D6		      D6
	     +12	+16	     D7		      D7
	     GND	GND	      2		      ~E
	     GND	GND	    R/~W	     R/~W
	    INDEX      INDEX	   +8 VDC	    +8 VDC
	     ~NMI      ~FIRQ	   +8 VDC	    +8 VDC
	     ~IRQ	~IRQ	    1200b	    1200b
	     RS0	RS0	    600b	    4800b
	     RS1	RS1	    300b	     300b
	      D0	 D0	    150b	    9600b
	      D1	 D1	    110b	     110b
	      D2	 D2	   ~RESET	    ~RESET
	      D3	 D3	  ~I/O SEL	   ~I/O	SEL










































				  - 4 -



		FFFFuuuunnnnccccttttiiiioooonnnnaaaallll DDDDeeeessssccccrrrriiiippppttttiiiioooonnnn ---- 55550000----PPPPiiiinnnn	BBBBuuuussss LLLLiiiinnnneeeessss

       ~D0-	 The ~D0-~D7 lines carry inverted data bits 0 thru
       ~D7	 7 respectively	forming	8-bit data words which are
		 exchanged between the various boards within the
		 system.
       A15-	 The A15-A0 lines carry	address	bits 15	thru 0
       A0	 respectively forming 16-bit addresses which are
		 exchanged between the various boards within the
		 system.
       GND	 The GND line is the system's common power supply
		 and signal ground point.
       7-8	 The 7-8 VDC UNREG is the line to which	a +7 to	+8
       VDC	 volt DC unregulated power supply should be
       UNREG	 attached.  This voltage is then regulated down	to
       or +8	 +5 VDC	by independent regulators on the various
       VNR	 boards	within the system.
       -16,+16	 The -16 and +16 are lines to which an isolated
		 ground	-16 and	+16 power supply should	be
		 connected.  The voltages are necessary	for
		 generating the	currents required by 20ma.  current
		 loop and RS232	equipment in the serial	interfaces
		 and by	dynamic	memory boards.
       INDEX	 The INDEX is an unused	line and is provided so	the
		 pin on	each of	the male connectors may	be cut with
		 the corresponding female connector pins plugged,
		 preventing the	circuit	board from being plugged on
		 incorrectly.
       M.RDY	 MEMORY	READY is the wire-OR control line on the
		 bus that allows the processor to work with
		 peripheral devices slower than	the clock speed	of
		 the system.  It works by stretching the ~E phase
		 of the	clock for up to	10 microseconds.
       ~BUSY	 The ~BUSY line	is a wire-OR line on the bus that
		 goes low to deny external access to memory or
		 peripherals during a 6809 READ/MODIFY/WRITE cycle.
       ~IRQ	 The ~IRQ is the wire-OR maskable single-level
		 interrupt request line	feeding	the processor
		 board.
       ~FIRQ	 The ~FIRQ line	is the wire-OR maskable	single
		 level fast interrupt request line feeding the
		 processor board.
       ~Q	 The ~Q	line is	a new clock output line	the leads
		 ~E (formerly 2) by approximately 90o in phase.
		 Its high to low transitions indicate that the
		 address output	on the address output on the
		 address bus are valid.















				  - 5 -



       ~E	 The ~E	is the clock formerly known as 2.  Data	is
		 valid out of the processor during a write on the
		 falling edge of ~E and	is clocked into	the
		 processor during a read on the	rising edge of ~E.
       ~VMA	 The ~VMA line is a normally high line that goes
		 low when a valid processor address is output onto
		 the bus.
       R/~W	 The READ/~WRITE line establishes the direction	of
		 data flow on the eight	data lines, ~D0-~D7.  It is
		 high for a read from memory or	interface and is
		 low for a write to memory or interface.
       ~RESET	 The ~RESET line when low resets the registers
		 internal to the processor and interfaces, and
		 loads the ROM stored mini-operating system.  This
		 line is activated by a	one-shot when the system is
		 first powered up.
       BA	 The BUS AVAILABLE line	goes high acknowledging	a
		 processor halt, bus grant, or sync.
       BS	 The BUS STATUS	line goes high acknowledging a
		 halt, bus grant or interrupt.	The line along with
		 the BA	line may be used to determine the status of
		 the processor.	 BA and	BS are valid on	the falling
		 edge of Q.
		      BA  BS
		       0   1  normal
		       0   1  interrupt	acknowledge
		       1   0  sync acknowledge
		       1   1  halt acknowledge or bus grant
       ~HALT	 The wire-OR ~HALT line	when brought low halts the
		 processor and frees the system	information bus	for
		 external control.
       ~BUS	 The wire-OR ~BUS REQUEST line when brought low
       REQ	 tri-states the	bus for	short term DMA type data
		 transfers.  Unlike the	halt sequence, BUS REQ is
		 granted immediately.
       S3-S0	 The S3	thru S0	lines are extended address lines
		 for paged memory system.

		FFFFuuuunnnnccccttttiiiioooonnnnaaaallll DDDDeeeessssccccrrrriiiippppttttiiiioooonnnn ---- 33330000----PPPPiiiinnnn	BBBBuuuussss LLLLiiiinnnneeeessss
       RS2	 The RS2 (Register Select 2) is	the buffered A2
		 Address line.
       RS3	 The RS3 (Register Select 3) line is the buffered
		 A3 address line.
       -16,+16	 (same as 50-pin bus)
       GND	 (same as 50-pin bus)
       INDEX	 The INDEX is an unused	line and is provided so	the
		 pin on	each of	the male connectors may	be cut with
		 the corresponding female connector pins plugged,
		 preventing the	circuit	board from being plugged on
		 incorrectly.












				  - 6 -



       ~FIRQ	 (same as 50-pin bus)
       ~IRQ	 (same as 50-pin bus)
       RS0	 The RS0 (Register Select 0) line is the buffered
		 A0 address line.
       RS1	 The RS1 (Register Select 1) line is the buffered
		 A1 address line.
       D0-D7	 The D0-D7 Data	lines are inverted and buffered
		 50-pin	bus data lines ~D0-~D7.
       E	 E is the inverted and buffered	50-pin bus ~E line.
       R/~W	 The R/~W line is the buffered 50-pin bus R/~W
		 line.
       +8	 The +8	VDC line is electrically the same as the
       VDC	 50-pin	bus 7-8	VDC UNR	line.
       1200b,	 These lines carry the 16X baud	rate clocks for	the
       4800b,	 serial	interfaces used	in the system.	They carry
       300b,	 baud rate clocks of 1200, 4800, 300, 9600, and	110
       9600b,	 respectively.	When the High Baud option on the
       110b	 processor board is selected, they may carry clocks
		 for 4800, 19200, 1200,	38400, and 400 baud
		 respectively.
       ~RESET	 (same as 50-pin bus)
       ~I/O	 The ~I/O SELECT line is not a bus line	at all but
       SELECT	 an individually decoded line per 30-pin bus
		 interface slot	which is selected by appropriate
		 logic on the mother board to place the	30-pin
		 boards	in the address space of	the processor.
		 Each 30-pin bus card can respond to up	to 16
		 addresses (RS0-RS3).


					Joseph L. Wood, III
					AT&T Information Systems
					Laboratories, Holmdel
					(201) 834-3759
					<ariel!>titania!jlw