jaro@utecfa.UUCP (3124) (01/05/84)
The VLSI Research Group of the Department of Electrical Engineering at the University of Toronto would like to plan a seminar series that will be beginning shortly. The speakers at these seminars will be people from industry who are directly involved with research in Very Large Scale Integrated circuits, at all levels. The seminars will probably be held monthly beginning in January. I would like to hear from any prospective attendees who may have objections to the proposed scheduling of these seminars. We would like to schedule a specific time slot, on the same day every week, that could be used once a month for guest speakers. One proposed time slot is 13:00 to 14:00 (1pm to 2pm) on Mondays; another is 14:00 to 15:00 (2pm to 3pm). Please let me know of any conflicts in these time slots for any days of the week so we can satisfy as many attendees as possible. Please reply by mail to Jaro Pristupa ...utcsrgv!utecfa!jaro