scottt@tektronix.UUCP (Scott Trappe) (02/11/84)
The 68000 and 16032 each use four clock cycles to do a memory read/write in
the best case. Thus comparing clock rates will give a good indication of
bus bandwidth for these processors ONLY. However, the 68000 and 16032 do
not make equal use of the bus. The following compares the read access time
(as seen on the pins of processor) for both chips assuming a clock rate of
10 MHz. The information for the 68000 is based on the "MC68000L10 16-bit
Microprocessing Unit - Advance Information". The 16032 information was
derived from "NS16000 Data Book". I have done designs using both processors.
For the 68000, the worst case read access time is:
Tread = 2.5Tcyc - Tchslx - Tdicl
where:
Tread = read access time (from AS' low to time data must be valid)
Tcyc = clock period
Tchslx = Clock high to AS', DS', low (maximum)
Tdicl = Data in to clock low (setup time)
Tchslx is measured from the rising edge at the end of S1 (end of first clock
cycle). Tdicl is the time from when data must be valid until the falling edge
of the clock at S6 (half way through the fourth clock cycle). Thus the 2.5
clock periods in the equation. Plugging in the numbers yields:
Tread = 2.5(100ns) - 55ns - 15ns
= 180ns
This assumes a symmetrical 10Mhz clock. Decreasing the clock low time to the
minimum (and correspondingly increasing the clock high time) might add another
5-10ns to the access time. This also assumes that the DTACK' timing is met.
For the 16032, the worst case read access time is:
Tread = 3Tcp - Tadsa - Tadsw - Tdis
where:
Tread = read access time (from ADS' high to time data must be valid)
Tcp = clock period
Tadsa = ADS' inactive (low, maximum)
Tadsw = ADS' pulse width (minimum)
Tdis = data in to PHI2 low (setup time)
The rising edge of ADS' initiates a read cycle on the 16032. The rising
edge occurs Tadsa + Tadsw after the rising edge of PHI1 (start of first
clock cycle). The data must be valid Tdis before the falling edge of PHI2
in the third clock cycle. Thus the 3 clock periods. Plugging in the numbers:
Tread = 3(100ns) - 40ns - 35ns - 10ns
= 215ns
The sharp-eyed 16000 designers will notice that I making a couple of
assumptions in the 16000 timing:
(1) that the falling edge of PHI2 is coincident with the rising edge
of PHI1. If the 16201 TCU is used, there will be 5ns between the
falling edge of PHI2 and rising edge of PHI1. Thus Tread is reduced
by that amount.
(2) Tadsw is only specified as a MINIMUM in the 16000 data sheets, not
as a MAXIMUM. In my system I measured Tadsw to be consistently
40ns.
In light of these assumptions, a more realistic Tread for the 16000 is:
Tread (adjusted) = 205ns
Note that by changing the duty cycle of the 16000 clocks you can also
extend its read cycle by about 10-15ns.
The difference in access times is:
Tdifference = Tread (16032) - Tread (68000)
= 205ns - 180ns
= 25ns
CONCLUSIONS.
The 16000 and 68000 each take 4 clock cycles to do a memory access, so the
bus utilization is the same for identical clock rates. But the 16032 can
wait longer for a memory read than can the 68000, so slower memory can be
used. Alternatively, the 16032 can run faster and use the same speed
memory as the 68000. A 68000 running at 9MHz has about the same memory
read time as a 10MHz 16032. Conversely, an 11MHz 16032 has about the
same memory read time as a 10MHz 68000.