rling@uw-june (Robert Ling) (03/10/84)
Does anyone have any information or know of a source where I
could get some information on the following about the
NSC 16k series microprocessors and its slaves?
- There is an eight byte instruction queue in the Pc,
but there is no mention of any pipelineing in the
instruction decoding process.
- Their literature hints of a set of 'shadow' registers
which saves the states of other general registers when
an instruction is initiated. How many of these registers
are there and which of the general registers do they
save?
- The width of the micro-instruction word and the size of
the Control Store.
- Is the Floating Point Unit pipelined? (Since there is
a data queue)
Please reply to me directly. Any information would be greatly
appreciated.
If there is sufficient response, I will post a summary.
Robert Ling.
...decvax!microsoft!uw-beaver!uw-june!rling