dcs@gitpyr.UUCP (David Sowell) (03/07/85)
------
I have some questions about the NS32032's addressing modes:
What does the Scaled Index addressing option do when applied
to a Register addressing mode? In other words, what does
something like "MOVW R1[R3:B],R0" do?
What results from doing something like "ADDR R1,R0"?
I do not have a machine to try these out on, otherwise I would. I am
designing a high level assembly language for the 320xx family and I need
to know what is meant by the above constructions.
In the documentation I have (see below) nothing is said about the legality
of these constructions. It does say that Scaled Index may not be applied
to the Immediate addressing mode or another Scaled Index addressing mode.
I understand how Scaled Index works for the other combinations. I am
surprised that if the above constructions are meaningless, it is not stated
so in the documentation.
Admittedly, most of my documentation is old. More current manuals may
address this issue (sorry about the pun...). I have these documents:
NS16000 Microprocessor Family Reprint of Technical Articles (1980)
NS16000 Programmers's Reference Manual
(Feb. 1982)
NS32032-6,NS32032-10 High-Performance Microprocessors
(Preliminary Data Sheet, Feb. 1984)
NS16032 High-Performance Microprocessor
(Preliminary Data Sheet, Apr. 1982)
NS16201 Timing Control Unit (TCU)
(Preliminary Data Sheet, June 7, 1981, Rev. H)
NS16202 Interrupt Control Unit
(Preliminary Data Sheet, Oct. 1982)
NS16082 Memory Management Unit (MMU)
(Preliminary Data Sheet, Mar, 1982)
Thanks,
David Sowell
David C Sowell
Georgia Insitute of Technology, Atlanta Georgia, 30332
...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dcssteveg@hammer.UUCP (Steve Glaser) (03/08/85)
In article <200@gitpyr.UUCP> dcs@gitpyr.UUCP (David Sowell) writes: >------ > >I have some questions about the NS32032's addressing modes: > > What does the Scaled Index addressing option do when applied > to a Register addressing mode? In other words, what does > something like "MOVW R1[R3:B],R0" do? > > What results from doing something like "ADDR R1,R0"? > In both of these examples the "access class" for the register operand is "addr" (scaled index addressing mode overrides the access class and forces it to "addr"). Since taking the address of a register doesn't make much sense (unless you're a PDP-10 I guess), National defined this case to be equivalent to 0(Rn). In other words, MOVW R1[R3:B],R0 puts the contents of the word at location (R1+R3) into the low word of R0 (upper word of R0 is unchanged) and the instruction ADDR R1,R0 is equivalent to MOVD R1,R0. This stuff also happens for Top of Stack addressing mode. In access class "addr", it means 0(SP). This "strange behaviour" is a minor win for code density cause normally 0(Rn) costs at least 1 byte for the displacement (displacements are either 1, 2 or 4 bytes). Steve Glaser tektronix!steveg
doon@sdcrdcf.UUCP (Harry W. Reed) (03/08/85)
In article <200@gitpyr.UUCP> dcs@gitpyr.UUCP (David Sowell) writes: >------ > >I have some questions about the NS32032's addressing modes: > > What does the Scaled Index addressing option do when applied > to a Register addressing mode? In other words, what does > something like "MOVW R1[R3:B],R0" do? > > What results from doing something like "ADDR R1,R0"? > >I do not have a machine to try these out on, otherwise I would. I am >designing a high level assembly language for the 320xx family and I need >to know what is meant by the above constructions. > >In the documentation I have (see below) nothing is said about the legality >of these constructions. It does say that Scaled Index may not be applied >to the Immediate addressing mode or another Scaled Index addressing mode. >I understand how Scaled Index works for the other combinations. I am >surprised that if the above constructions are meaningless, it is not stated >so in the documentation. > >Admittedly, most of my documentation is old. More current manuals may >address this issue (sorry about the pun...). I have these documents: > > NS16000 Microprocessor Family Reprint of Technical Articles (1980) > > NS16000 Programmers's Reference Manual > (Feb. 1982) > > NS32032-6,NS32032-10 High-Performance Microprocessors > (Preliminary Data Sheet, Feb. 1984) > > NS16032 High-Performance Microprocessor > (Preliminary Data Sheet, Apr. 1982) > > NS16201 Timing Control Unit (TCU) > (Preliminary Data Sheet, June 7, 1981, Rev. H) > > NS16202 Interrupt Control Unit > (Preliminary Data Sheet, Oct. 1982) > > NS16082 Memory Management Unit (MMU) > (Preliminary Data Sheet, Mar, 1982) > > > Thanks, > David Sowell > > >David C Sowell >Georgia Insitute of Technology, Atlanta Georgia, 30332 >...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dcs David: I, like you, am developing software for the 32000 without any hardware to try things on. In my case I'm writing a cross-assembler for the 32000 family that will be used in conjunction with a port of Pcc. I to have wondered about the results of such things as ... r0[r1:q]. I think (and hope) the 32000's microcode realizes that this is rather meaningless. It is indeed odd that this form of scaled indexed addressing is allowed. I'm glad to know that i'm not alone in not knowing what that type of construct does. Cordially, Harry Reed
mikel@bmcg.UUCP (Mike Lesher) (03/10/85)
[Row, row, row your bits, gently down the stream...] In article <> dcs@gitpyr.UUCP (David Sowell) writes: >------ > >I have some questions about the NS32032's addressing modes: > > What does the Scaled Index addressing option do when applied > to a Register addressing mode? In other words, what does > something like "MOVW R1[R3:B],R0" do? > > What results from doing something like "ADDR R1,R0"? > >I do not have a machine to try these out on, otherwise I would. I am >designing a high level assembly language for the 320xx family and I need >to know what is meant by the above constructions. > > >David C Sowell >Georgia Insitute of Technology, Atlanta Georgia, 30332 >...!{akgua,allegra,amd,hplabs,ihnp4,seismo,ut-ngp}!gatech!gitpyr!dcs I have tried these instruction on our system an found: MOVW R1[R3:B],R0 = MOVW @(R1+R2), R0 ADDR R1,R0 = MOVD R1, R0 I hope this answers your questions. Mike Lesher Burroughs ASG, San Diego, CA. (..!bmcg!mikel)
wjafyfe@watmath.UUCP (Andy Fyfe) (03/10/85)
The following is taken from "NS16000 Instruction Set Reference Manual",
dated August, 1983 (and (c) National Semiconductor).
From the section on access classes, table 4-1
----------------+----------------------------------------------
| Access Class
Addressing +----------------------------------------------
Mode | read write rmw addr regaddr
----------------+----------------------------------------------
Register | Rn,Fn Rn,Fn Rn,Fn (Rn) Rn,Fn
Immediate | legal ----- ----- ----- -----
Top Of Stack | Push Pop (SP) (SP) (SP)
----------------+----------------------------------------------
Note (2): Using Scaled Indexing in an addressing mode overrides
the access class and forces it to addr.
Thus, for example, R0[R1:B] means (R0)[R1:B].
Hope this answers your question.
--Andy Fyfe ...!{decvax, allegra, ihnp4, et. al}!watmath!wjafyfe
wjafyfe@waterloo.csnet